L64704 LSI Logic Corporation, L64704 Datasheet - Page 157

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 7.12
Block Diagram of
Deinterleaver Core
7.2.2
Deinterleaver
Output
Equation 7.2
Figure 7.13
Deinterleaver Output
Example
Internal
Output
Strobe
Input
Data
Data
1
Byte Stream
The Deinterleaver receives the rearranged byte stream and inverts the
interleaver’s function to reconstruct the original byte stream. The internal
strobes indicate the block boundaries that the Deinterleaver must
recover.
The Deinterleaver outputs the original byte stream after a delay given by:
Figure 7.13
{2 x 3 x 2 + 1} x 8 + 1 = 105 clock cycles. Notice that the delay from the
first input byte to the first valid output byte is indeed 105 clock cycles.
Deinterleaver Module
Delay
Interleaved
Strobes
Control
4
Frame
=
shows an example in which the total delay is
B 1
OCLK
105 clock cycles
8
–
7
B
2
N B
Control Module
RAM based
Delay Lines
A
+
5
1
8
+
D
1
8
1
8
3
2
1
Control Strobes
to Pipeline
Data Path
Deinterleaved
Byte Stream
3
B
4
6
5
4
6
7-13