MAX1981A Maxim Integrated Products, MAX1981A Datasheet - Page 15

• Manufacturer Part Number: MAX1981A
• Description: (MAX1907A / MAX1981A) Quick-PWM Master Controllers
• Manufacturer: Maxim Integrated Products

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21–26
Positioned CPU Core Power Supplies (IMVP-IV)
PIN
19
20
27
28
29
30
31
32
33
34
35
36
SYSPOK
Quick-PWM Master Controllers for Voltage-
DPSLP
D5–D0
NAME
PGND
DDO
CSN
V
BST
SUS
DH
DL
V+
LX
DD
______________________________________________________________________________________
Negative Current-Limit Input. Connect to the negative terminal of the current-sense resistor.
Deep-Sleep Control Input. When DPSLP is low the system enters the deep-sleep state and the regulator
applies the appropriate deep-sleep offset. The MAX1907A/MAX1981A adds the offset measured at the POS
and NEG pins to the output. 32 clock cycles after the deep-sleep transition is completed, DDO goes low
(see the Driver Disable and Low-Power Pulse Skipping section). Another 32 clock cycles later, the
MAX1907A/MAX1981A is allowed to enter pulse-skipping operation.
Low-Voltage VID DAC Code Inputs. D0 is the LSB, and D5 is the MSB of the internal 6-bit VID DAC (Table
4). The D0–D5 inputs do not have internal pullups. These 1V logic inputs are designed to interface directly
with the CPU. In all normal active modes (modes other than suspend and boot), the output voltage is set by
the VID code indicated by the D0–D5 logic-level voltages on D0–D5. In suspend mode (SUS = high), the
decoded state of the four-level S0–S2 inputs sets the output voltage. In boot mode (see the Power-Up
Sequence section), the decoded state of the four-level B0–B2 inputs set the output voltage.
Driver-Disable Output. This TTL-logic output can be used to disable the driver outputs on slave-switching
regulator controllers. This forces a high-impedance condition and makes it possible for the
MAX1907A/MAX1981A master controller to operate in low current SKIP mode. DDO goes low 32 R
clock cycles after the MAX1907A/MAX1981A completes a transition to the suspend mode or deep-sleep
voltage (see the Driver Disable and Low-Power Pulse Skipping section). Another 30 clock cycles later, the
MAX1907A/MAX1981A enters automatic pulse-skipping operation.
Power Ground. Ground connection for the DL gate driver.
Low-Side Gate Driver Output. DL swings from PGND to V
MAX1907A/MAX1981A powers down (SHDN = GND) or when the controller detects a fault. The MAX1981A
does not include overvoltage protection.
Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (4.5V to 5.5V). Bypass to
PGND with a 1µF or greater ceramic capacitor, as close to the IC as possible.
Boost Flying Capacitor Connection. An optional resistor in series with BST allows the DH pullup current to
be adjusted.
Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It connects to the
skip-mode zero-crossing comparator.
High-Side Gate Driver. Output swings LX to BST.
Battery Voltage Sense Connection. Used only for PWM one-shot timing. DH on-time is inversely proportional
to input voltage over a range of 2V to 28V.
Suspend-Mode Control Input. When SUS is high the regulator slews to the suspend voltage level. This level
is set with four-level logic signals at the S0–S2 inputs. 32 clock cycles after the transition to the suspend-
mode voltage is completed, DDO goes low (see the Driver Disable and Low-Power Pulse Skipping section).
Another 32 clock cycles later, the MAX1907A/MAX1981A is allowed to enter pulse-skipping operation.
System Power-Good Input. Primarily, SYSPOK serves as the wired NOR junction of the open-drain power-
good signals for the V
MAX1907A/MAX1981A and sets the fault latch. Toggle SHDN or cycle V
controller.
CCP
and V
CCMCH
supplies. A falling edge on SYSPOK shuts down the
FUNCTION
DD
Pin Description (continued)
. DL is forced high after the
CC
power below 1V to restart the
TIME
15