MAX1981A Maxim Integrated Products, MAX1981A Datasheet - Page 22

• Manufacturer Part Number: MAX1981A
• Description: (MAX1907A / MAX1981A) Quick-PWM Master Controllers
• Manufacturer: Maxim Integrated Products

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Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Forced-PWM operation comes at a cost: the no-load 5V
bias supply current remains between 10mA to 40mA,
depending on the external MOSFETs and switching fre-
quency. To maintain high efficiency under light load
conditions, the MAX1907A/MAX1981A automatically
switches to the low-power pulse skipping control
scheme after entering suspend or deep-sleep mode.
During all output voltage and mode transitions, the
MAX1907A/MAX1981A uses forced-PWM operation in
order to ensure fast, accurate transitions. Since forced-
PWM operation disables the zero-crossing comparator,
the inductor current reverses under light loads, quickly
discharging the output capacitors. The controller main-
tains forced-PWM operation for 30 clock cycles (set by
R
to guarantee the output voltage settles properly before
entering pulse-skipping operation.
During deep-sleep mode (DPSLP = low) or low-power
suspend (SUS = high), the MAX1907A/MAX1981A uses
an automatic pulse-skipping control scheme.
For deep-sleep mode, when the CPU pulls DPSLP low,
the MAX1907A/MAX1981A shifts the output voltage to
incorporate the offset voltage set by the POS and NEG
inputs. The controller pulls the driver-disable output
(DDO) low 32 R
Another 30 R
MAX1981A enters low-power operation, allowing auto-
matic pulse skipping under light loads. When the CPU
drives DPSLP high, the MAX1907A/MAX1981A immedi-
ately enters forced-PWM operation, forces DDO high,
and eliminates the output offset, slewing the output to
the operating voltage set by the D0–D5 inputs. When
either DPSLP transition occurs, the MAX1907A/
MAX1981A forces IMVPOK high and CLKEN low for 32
R
When entering suspend mode (SUS driven high), the
MAX1907A/MAX1981A slews the output down to the
suspend output voltage set by SO–S2 inputs. 32 R
clock cycles after the slew-rate controller reaches the
last DAC code (see the Output Voltage Transition
Timing section), the driver-disable output (DDO) is
asserted low. After another 30 R
MAX1907A/MAX1981A enters low-power operation,
allowing pulse skipping under light loads. When the
CPU pulls SUS low, the MAX1907A/MAX1981A immedi-
ately enters forced-PWM operation, forces DDO high,
and slews the output up to the operating voltage set by
the D0–D5 inputs. When either SUS transition occurs,
the MAX1907A/MAX1981A blanks IMVPOK and CLKEN,
preventing IMVPOK from going low and CLKEN from
22
TIME
TIME
______________________________________________________________________________________
) after the controller sets the last DAC code value
clock cycles.
TIME
TIME
clock cycles later, the MAX1907A/
clock cycles after DPSLP goes low.
Low-Power Pulse Skipping
TIME
clock cycles, the
TIME
going high. The blanking remains until the slew-rate
controller has reached the last DAC code and 32
RTIME clock pulses have passed.
In multiphase applications, the driver-disable signal is
used to force one or more slave regulators into a high-
impedance state. When the master’s DDO output is dri-
ven low, the slave controller with driver disable
(MAX1980) forces its DL (SLAVE) and DH (SLAVE) gate
drivers low, effectively disabling the slave controller.
Disabling the slave controller for single-phase opera-
tion allows the MAX1907A/MAX1981A to enter low-
power pulse-skipping operation under low-power
conditions, improving light-load efficiency. When DDO
is driven high, the slave controller (MAX1980) enables
the drivers, allowing normal forced-PWM operation.
In skip mode (SUS = high, or DPSLP = low), an inherent
automatic switchover to PFM takes place at light loads
(Figure 3). This switchover is effected by a comparator
that truncates the low-side switch on-time at the induc-
tor current’s zero crossing. The zero-crossing compara-
tor senses the inductor current across the low-side
MOSFET. Once V
the comparator forces DL low
nism causes the threshold between pulse-skipping
PFM and non-skipping PWM operation to coincide with
the boundary between continuous and discontinuous
inductor-current operation. The load-current level at
which PFM/PWM crossover occurs, I
equal to 1/2 the peak-to-peak ripple current, which is a
function of the inductor value
range of 8V to 24V, this threshold is relatively constant,
with only a minor dependence on battery voltage:
where K is the on-time scale factor (Table 3). For exam-
ple, in the standard application circuit this becomes:
The crossover point occurs at a lower value if a swing-
ing (soft-saturation) inductor is used. The switching
waveforms may appear noisy and asynchronous when
light loading causes pulse-skipping operation, but this
is a normal operating condition that results in high light-
load efficiency. Trade-offs in PFM noise vs. light-load
efficiency are made by varying the inductor value.
Generally, low inductor values produce a broader effi-
Automatic Pulse-Skipping Switchover
I
⎛
⎜
⎝
LOAD SKIP
1 3
2
.
×
V
(
0 68
×
.
3 3
LX
)
.
μ
=
μ
H
- VP
⎛
⎜
⎝
s
V
⎞
⎟
⎠
OUT
⎛
⎜
⎝
2
12 0
GND
L
K
.
12 0
⎞
⎟
⎠
V
⎛
⎜
⎝
(Figure
drops below 4mV (typ),
(Figure
.
V
−
BATT
V
1 3
.
V
BATT
V
−
⎞
⎟ =
⎠
4). For a battery
V
2). This mecha-
OUT
LOAD(SKIP)
2 8
.
⎞
⎟
⎠
A
, is