MAX1981A Maxim Integrated Products, MAX1981A Datasheet - Page 31

• Manufacturer Part Number: MAX1981A
• Description: (MAX1907A / MAX1981A) Quick-PWM Master Controllers
• Manufacturer: Maxim Integrated Products

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The MAX1907A/MAX1981A has two unique internal
DAC input multiplexers (muxes) that can select one of
three different DAC code settings for different proces-
sor states. On startup, the controller selects the DAC
code from the B0–B2 input decoder. Once SYSPOK
goes high and the MAX1907A/MAX1981A properly reg-
ulates to the boot voltage, a second multiplexer selects
the DAC code from either D0–D5 (SUS = low) or S0–S2
(SUS = high), depending on the SUS state (Figure 7).
When the processor enters low-power suspend mode,
the system uses a lower supply voltage to reduce
power consumption. The MAX1907A/MAX1981A
include independent suspend-mode output voltage
codes set by the four-level inputs S0–S2. When the
CPU suspends operation, SUS is driven high, overrid-
ing the 6-bit VID DAC code set by D0–D5. The master
controller slews the output to the selected suspend-
mode voltage. During the transition, the MAX1907A/
MAX1981A asserts forced-PWM operation until 62
R
es the suspend-mode voltage.
When SUS is low, the output voltage is dynamically
controlled by the 6-bit VID DAC inputs (D0–D5).
The MAX1907A/MAX1981A is designed to perform
mode transitions in a controlled manner, automatically
minimizing input surge currents. This feature allows the
circuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output volt-
age level with the lowest possible peak currents for a
given output capacitance. This makes the IC ideal for
IMVP-IV CPUs.
At the beginning of an output voltage transition, the
MAX1907A/MAX1981A blanks the IMVPOK and CLKEN
outputs, preventing them from changing states.
IMVPOK and CLKEN remain blanked during the transi-
tion and is re-enabled 32 clock cycles after the slew-
rate controller has set the final DAC code value. The
slew-rate clock frequency (set by resistor R
be set fast enough to ensure that the transition is com-
pleted within the maximum allotted time.
The slew-rate controller transitions the output voltage in
16mV increments during power-up, soft-shutdown, and
suspend-mode transitions. The total time for a transition
depends on R
TIME
Positioned CPU Core Power Supplies (IMVP-IV)
clock cycles after the slew-rate controller reach-
Quick-PWM Master Controllers for Voltage-
Output Voltage Transition Timing
TIME
______________________________________________________________________________________
, the voltage difference, and the
Internal Multiplexers
Suspend Mode
TIME
) must
accuracy of the MAX1907A/MAX1981As’ slew-rate
clock, and is not dependent on the total output capaci-
tance. The greater the output capacitance, the higher
the surge current required for the transition. The
MAX1907A/MAX1981A automatically control the current
to the minimum level required to complete the transition
in the calculated time, as long as the surge current is
less than the current limit set by ILIM. The transition
time is given by:
where f
original DAC setting, and V
The additional 2 clock cycles on the falling edge time
are due to internal synchronization delays. See Time
Frequency Accuracy in the Electrical Characteristics for
f
The practical range of R
sponding to 1.6µs to 15.6µs per 16mV step. Although
the DAC takes discrete 16mV steps, the output filter
makes the transitions relatively smooth. The average
inductor current required to make an output voltage
transition is:
The overvoltage protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The output voltage is continuously monitored for over-
voltage. If the actual output voltage exceeds the set
output voltage by more than 13% (min), OVP is trig-
gered and the circuit shuts down. IMVPOK is pulled low
and CLKEN is driven high immediately. The DL low-side
gate-driver output is then latched high until SHDN is
toggled or V
turns on the synchronous-rectifier MOSFET with 100%
duty and, in turn, rapidly discharges the output filter
capacitor and forces the output to ground. If the condi-
tion that caused the overvoltage (such as a shorted
high-side MOSFET) persists, the battery fuse will blow.
OVP can be defeated through the NO FAULT test mode
(see the NO FAULT Test Mode section).
SLEW
t
t
SLEW
SLEW
accuracy.
≈
≈
SLEW
f
f
SLEW
SLEW
1
1
CC
= 320kHz
I
L
⎡
⎢
⎣
⎛
⎜
⎝
Output Overvoltage Protection
power is cycled below 1V. This action
≅ C
⎛
⎜
⎝
V
V
NEW
OLD
OUT
16
16
mV
TIME
−
✕
−
mV
✕
V
V
16mV
NEW
OLD
47kΩ / R
NEW
is 23.5kΩ to 235kΩ corre-
⎞
⎟
⎠
is the new DAC setting.
⎞
⎟ +
⎠
(MAX1907A Only)
✕
for V
f
SLEW
2
⎤
⎥
⎦
TIME
OUT
for V
, V
ri
OUT
sin
OLD
g
falling
is the
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