MAX1981A Maxim Integrated Products, MAX1981A Datasheet - Page 24

• Manufacturer Part Number: MAX1981A
• Description: (MAX1907A / MAX1981A) Quick-PWM Master Controllers
• Manufacturer: Maxim Integrated Products

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Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
pling between LX and DL created by the MOSFETs’
gate-to-drain capacitance (C
(C
exceed the following minimum threshold voltage:
Lot-to-lot variation of the threshold voltage may cause
problems in marginal designs. Typically, adding
4700pF between DL and power ground close to the
low-side MOSFETs greatly reduces coupling. Due
should not exceed 22nF of total gate capacitance to
prevent excessive turn-off delays. Alternatively, adding
a resistor less than 5Ω in series with BST may remedy
the problem by increasing the turn-on time of the high-
side MOSFET without degrading the turn-off time
(Figure 5).
The MAX1907A/MAX1981A includes a dedicated oper-
ational amplifier for adding gain to the voltage position-
ing sense path. The voltage positioning gain allows the
use of low-value, current-sense resistors in order to
minimize power dissipation. This 3MHz gain-bandwidth
amplifier was designed with low offset voltage (70µV,
typ) to meet the IMVP-IV output accuracy requirements.
The inverting (OAIN-) and noninverting (OAIN+) inputs
are used to differentially sense the voltage across the
voltage-positioning sense resistor. The op amp’s output
is internally connected to the regulator’s feedback input
(FB). The op amp should be configured as a noninvert-
ing, differential amplifier as shown in Figure 1. The volt-
age positioning slope is set by properly selecting the
feedback resistor connected from FB to OAIN- (see the
Setting Voltage Positioning section). For applications
using a slave controller, additional differential input
resistors (summing configuration) should be connected
to the slave’s voltage-positioning sense resistor (Figure
1). Summing together both the master and slave cur-
rent-sense signals ensures that the voltage-positioning
slope will remain constant when the slave controller is
disabled.
In applications that do not require voltage-positioning
gain, the amplifier can be disabled by connecting the
OAIN- pin directly to V
put becomes high-impedance, guaranteeing that the
unused amplifier will not corrupt the FB input signal.
The logic threshold to disable the op amp is approxi-
mately V
24
ISS
______________________________________________________________________________________
-C
RSS
CC
), and additional board parasitics should not
- 1V.
V
Voltage Positioning Amplifier
GS TH
(
CC
)
<
. The disabled amplifier’s out-
V
IN
⎛
⎜
⎝
C
C
RSS
RSS
ISS
⎞
⎟
⎠
), gate-to-source
Power-on reset (POR) occurs when V
approximately 2V, resetting the fault latch and preparing
the PWM for operation. V
(UVLO) circuitry inhibits switching, and forces the DL
gate driver high (to enforce output overvoltage protec-
tion). When V
sampled and the output voltage begins to slew to the
boot voltage
For automatic startup, the battery voltage should be
present before V
attempts to bring the output into regulation without the
battery voltage present, the fault latch will trip. The
SHDN pin can be toggled to reset the fault latch.
During start-up, the V
gate driver high and the DH gate driver low, inhibiting
switching until an adequate supply voltage is reached.
Once V
at the trigger input initiate a corresponding on-time
pulse (see the On-Time One-Shot section).
If the V
there is not enough supply voltage to make valid deci-
sions. To protect the output from overvoltage faults, DL is
forced high in this mode to force the output to ground.
Figure 5. High-Side Gate-Driver Boost Circuitry
(R
NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT
CAN CAUSE SHOOT-THROUGH CURRENTS.
MAX1907A
MAX1981A
BST
)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING
CC
CC
V
DD
voltage drops below 4.25V, it is assumed that
rises above 4.25V, valid transitions detected
(Table
CC
PGND
V
BST
DH
DL
DD
LX
rises above 4.25V, the DAC inputs are
CC
Input Undervoltage Lockout
7).
(R
. If the MAX1907A/MAX1981A
CC
BST
)*
UVLO circuitry forces the DL
(C
NL
CC
)*
D
C
BST
C
BYP
BST
undervoltage lockout
Power-On Reset
CC
N
N
H
L
rises above
INPUT
(V
L
IN
)