AT91M40400-25C ATMEL Corporation, AT91M40400-25C Datasheet - Page 14

• Manufacturer Part Number: AT91M40400-25C
• Description: 16/32-bit Microcontroller, 2.7V to 3.6V Operating Range
• Manufacturer: ATMEL Corporation

Read Protocols
The EBI provides two alternative protocols for external
memory read access: standard and early read. The differ-
ence between the two protocols lies in the timing of the
NRD (read cycle) waveform.
The protocol is selected by the DRP field in EBI_MCR
(Memory Control Register) and is valid for all memory
devices. Standard read protocol is the default protocol after
reset.
Note: In the following waveforms and descriptions, NRD
represents NRD and NOE since the two signals have the
same waveform. Likewise, NWE represents NWE, NWR0
and NWR1 unless NWR0 and NWR1 are otherwise repre-
sented. ADDR represents A0-A23 and/or A1-A23.
Standard Read Protocol
Standard read protocol implements a read cycle in which
NRD and NWE are similar. Both are active during the sec-
ond half of the clock cycle. The first half of the clock cycle
allows time to ensure completion of the previous access as
well as the output of address and NCS before the read
cycle begins.
During a standard read protocol external memory access,
NCS is set low and ADDR is valid at the beginning of the
access while NRD goes low only in the second half of the
master clock cycle to avoid bus conflict (see Figure 13).
NWE is the same in both protocols. NWE always goes low
in the second half of the master clock cycle (see Figure 14).
Early Read Protocol
Early read protocol provides more time for a read access
from the memory by asserting NRD at the beginning of the
clock cycle. In the case of successive read cycles in the
same memory, NRD remains active continuously. Since a
read cycle normally limits the speed of operation of the
external memory system, early read protocol can allow a
faster clock frequency to be used. However, an extra wait
state is required in some cases to avoid contentions on the
external bus.
Early Read Wait State
In early read protocol, an early read wait state is automati-
cally inserted when an external write cycle is followed by a
read cycle to allow time for the write cycle to end before the
subsequent read cycle begins (see Figure 15). This wait
state is generated in addition to any other programmed wait
states (i.e. data float wait).
No wait state is added when a read cycle is followed by a
write cycle, between consecutive accesses of the same
type or between external and internal memory accesses.
Early read wait states affect the external bus only. They do
not affect internal bus timing.
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AT91M40400
Figure 13. Standard Read Protocol
Figure 14. Early Read Protocol
Figure 15. Early Read Wait State
ADDR
MCKI
NWE
NCS
NRD
or
or
ADDR
ADDR
MCKI
MCKI
NWE
NWE
NCS
NRD
NCS
NRD
write cycle
early read wait
read cycle