AT91M40400-25C ATMEL Corporation, AT91M40400-25C Datasheet - Page 5

• Manufacturer Part Number: AT91M40400-25C
• Description: 16/32-bit Microcontroller, 2.7V to 3.6V Operating Range
• Manufacturer: ATMEL Corporation

Architectural Overview
The AT91M40400 architecture consists of two main buses,
the Advanced System Bus (ASB) and the Advanced
Peripheral Bus (APB). The ASB is designed for maximum
performance. It interfaces the processor with the on-chip
32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is
designed for accesses to on-chip peripherals and is opti-
mized for low power consumption. The AMBA Bridge pro-
vides an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC) transfers data
between the on-chip USARTs and the on and off-chip
memories without processor intervention. Most importantly,
the PDC removes the processor interrupt handling over-
head and significantly reduces the number of clock cycles
required for a data transfer. It can transfer up to 64k contig-
uous bytes without reprogramming the starting address. As
a result, the performance of the microcontroller is increased
and the power consumption reduced.
The AT91M40400 peripherals are designed to be pro-
grammed with a minimum number of instructions. Each
peripheral has a 16K byte address space allocated in the
upper 3M bytes of the 4G byte address space. Except for
the interrupt controller, the peripheral base address is the
lowest address of its memory space. The peripheral regis-
ter set is composed of control, mode, data, status and inter-
rupt registers.
To maximize the efficiency of bit manipulation, frequently
written registers are mapped into three memory locations.
The first address is used to set the individual register bits,
the second resets the bits and the third address reads the
value stored in the register. A bit can be set or reset by writ-
ing a one to the corresponding position at the appropriate
address. Writing a zero has no effect. Individual bits can
thus be modified without having to use costly read-modify-
write and complex bit manipulation instructions and without
having to store-disable-restore the interrupt state.
All of the external signals of the on-chip peripherals are
under the control of the Parallel I/O controller. The PIO con-
troller can be programmed to insert an input filter on each
pin or generate an interrupt on a signal change. After reset,
the user must carefully program the PIO Controller in order
to define which peripheral signals are connected with off-
chip logic.
The ARM7TDMI processor operates in little-endian mode
in the AT91M40400 microcontroller. The processor’s inter-
nal architecture and the ARM and Thumb instruction sets
are described in the ARM7TDMI Datasheet. The memory
map and the on-chip peripherals are described in the sub-
sequent sections of this datasheet. Electrical characteris-
tics are documented in a separate datasheet entitled
“AT91M40400 Electrical and Mechanical Characteristics”.
The ARM Standard In-Circuit-Emulation debug interface is
supported via the ICE port of the AT91M40400 microcon-
troller. (This is not a standard IEEE 1149.1 JTAG Boundary
Scan interface)
PDC: Peripheral Data Controller
The AT91M40400 has a 4-channel PDC dedicated to the
two on-chip USARTs. One PDC channel is connected to
the receiving channel and one to the transmitting channel
of each USART.
The user interface of a PDC channel is integrated in the
memory space of each USART channel. It contains a 32-bit
address pointer register and a 16-bit byte count register.
When the programmed number of bytes are transferred, an
end of transfer interrupt is generated by the corresponding
USART. See the section describing the USART beginning
on page 64 for more details on PDC operation and pro-
gramming.
AT91M40400
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