AT91M40400-25C ATMEL Corporation, AT91M40400-25C Datasheet - Page 8

• Manufacturer Part Number: AT91M40400-25C
• Description: 16/32-bit Microcontroller, 2.7V to 3.6V Operating Range
• Manufacturer: ATMEL Corporation

Initialization
Reset
Reset initializes the user interface registers to their default
states as defined in the peripheral sections of this
datasheet and forces the ARM7TDMI to perform the next
instruction fetch from address zero. Except for the program
counter the ARM core registers do not have defined reset
states. When reset is active, the inputs of the AT91M40400
must be held at valid logic levels. The EBI address lines
drive low during reset.
NRST Pin
NRST is the active low reset input. It is asserted asynchro-
nously, but exit from reset is synchronized internally to
MCKI. MCKI must be active within specification for a mini-
mum of 10 clock cycles up to the rising edge of NRST, to
ensure correct operation.
The pins BMS and NTRI are sampled during the 10 clock
cycles just prior to the rising edge of NRST.
Watchdog Reset
The internally generated watchdog reset has the same
effect as the NRST pin, except that the pins BMS and TRI
are not sampled. Boot Mode and Tristate Mode are not
updated. The NRST pin has priority if both types of reset
coincide.
Boot Mode Select
The input level on the BMS pin during the last 10 clock
cycles before the rising edge of NRST selects the type of
Boot memory. Boot operation is described on page 13.
BMS must be driven to a valid logic value during reset.
The Boot Mode depends on BMS and whether the
AT91M40400 has on-chip non-volatile memory (NVM). See
Table 2 below.
The correct logic level on BMS can be ensured with a resis-
tor (pull-up or pull-down). See “AT91M40400 Electrical and
Mechanical Characteristics” for the resistor value specifica-
tion.
The BMS pin is multiplexed with Parallel I/O P24 which can
be programmed after reset like any standard PIO.
Table 2. Boot Mode Select
BMS
1
0
8
Architecture
No NVM
NVM on-chip
All
AT91M40400
Boot Mode
External 8-bit memory on NCS0
Internal 32-bit NVM
External 16-bit memory on NCS0
Emulation Functions
Tristate Mode
The AT91M40400 provides a Tristate Mode, which is used
for debug purposes in order to connect an emulator probe
to an application board. In Tristate Mode the AT91M40400
continues to function, but all the output pin drivers are
tristated.
To enter Tristate Mode, the pin NTRI must be held low dur-
ing the last 10 clock cycles before the rising edge of NRST.
For normal operation the pin NTRI must be held high during
reset, by a resistor of up to 400k ohm. NTRI must be driven
to a valid logic value during reset.
NTRI is multiplexed with Parallel I/O P21 and USART 1
serial data transmit line TXD1.
Standard RS232 drivers generally contain internal 400K
Ohm pull-up resistors. If TXD1 is connected to one of
these drivers this pull-up will ensure normal operation, with-
out the need for an additional external resistor.
JTAG/ICE Debug Mode
ARM Standard Embedded In Circuit Emulation is sup-
ported via the JTAG/ICE port. It is connected to a host
computer via an external ICE Interface.
In ICE Debug Mode the ARM core responds with a non-
JTAG chip ID which identifies the core to the ICE system.
This is not IEEE 1149.1 JTAG compliant.