AT91M40400-25C ATMEL Corporation, AT91M40400-25C Datasheet - Page 37

• Manufacturer Part Number: AT91M40400-25C
• Description: 16/32-bit Microcontroller, 2.7V to 3.6V Operating Range
• Manufacturer: ATMEL Corporation

Spurious Interrupt
When the AIC asserts the NIRQ line, the ARM7TDMI
enters IRQ mode and the interrupt handler reads the IVR. It
may happen that the AIC de-asserts the NIRQ line after the
core has taken into account the NIRQ assertion and before
the read of the IVR.
This behavior is called a Spurious Interrupt.
The AIC is able to detect these Spurious Interrupts and
returns the Spurious Vector when the IVR is read. The Spu-
rious Vector can be programmed by the user when the vec-
tor table is initialized.
A spurious interrupt may occur in the following cases:
•
•
The same mechanism of spurious interrupt occurs if the
ARM7TDMI reads the IVR (application software or ICE)
when there is no interrupt pending. This mechanism is also
valid for the FIQ interrupts.
Once the AIC enters the spurious interrupt management, it
asserts neither the NIRQ nor the NFIQ lines to the
ARM7TDMI as long as the spurious interrupt is not
acknowledged. Therefore, it is mandatory for the Spurious
Interrupt Service Routine to acknowledge the “spurious”
behavior by writing to the AIC_EOICR (End of Interrupt)
before returning to the interrupted software. It also can per-
form other operation(s), e.g. trace possible undesirable
behavior.
Protect Mode
The Protect Mode permits reading of the Interrupt Vector
Register without performing the associated automatic oper-
ations. This is necessary when working with a debug sys-
tem.
When a Debug Monitor or an ICE reads the AIC User Inter-
face, the IVR could be read. This would have the following
consequences in normal mode:
•
•
In either case, an End of Interrupt Command would be nec-
essary to acknowledge and to restore the context of the
AIC. This operation is generally not performed by the
debug system. Hence the debug system would become
strongly intrusive, and could cause the application to enter
an undesired state.
This is avoided by using Protect Mode.
With any sources programmed to be level sensitive, if the
interrupt signal of the AIC input is de-asserted at the
same time as it is taken into account by the ARM7TDMI.
If an interrupt is asserted at the same time as the
software is disabling the corresponding source through
AIC_IDCR (this can happen due to the pipelining of the
ARM core).
If an enabled interrupt with a higher priority than the
current one is pending, it would be stacked.
If there is no enabled pending interrupt, the spurious
vector would be returned.
The Protect Mode is enabled by setting the AIC bit in the
SF Protect Mode Register (see SF: Special Function Reg-
isters on page 145).
When Protect Mode is enabled, the AIC performs interrupt
stacking only when a write access is performed on the
AIC_IVR. Therefore, the Interrupt Service Routines must
write (arbitrary data) to the AIC_IVR just after reading it.
The new context of the AIC, including the value of the Inter-
rupt Status Register (AIC_ISR), is updated with the current
interrupt only when IVR is written.
An AIC_IVR read on its own (e.g. by a debugger), modifies
neither the AIC context nor the AIC_ISR.
Extra AIC_IVR reads performed in between the read and
the write can cause unpredictable results. Therefore, it is
strongly recommended not to set a breakpoint between
these 2 actions, nor to stop the software.
The debug system must not write to the AIC_IVR as this
would cause undesirable effects.
The following table shows the main steps of an interrupt
and the order in which they are performed according to the
mode:
Notes:
Action
Calculate active interrupt
(higher than current or spurious)
Determine and return the vector of
the active interrupt
Memorize interrupt
Push on internal stack the current
priority level
Acknowledge the interrupt
No effect
1. NIRQ de-assertion and automatic interrupt clearing if
2. Note that software which has been written and
(2)
the source is programmed as level sensitive
debugged using Protect Mode will run correctly in
Normal Mode without modification. However in Nor-
mal Mode the AIC_IVR write has no effect and can
be removed to optimize the code.
(1)
AT91M40400
AIC_IVR
AIC_IVR
AIC_IVR
AIC_IVR
AIC_IVR
AIC_IVR
Normal
Mode
Read
Read
Read
Read
Read
Write
AIC_IVR
AIC_IVR
AIC_IVR
AIC_IVR
AIC_IVR
Protect
Mode
Read
Read
Read
Write
Write
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