AT91M40400-25C ATMEL Corporation, AT91M40400-25C Datasheet - Page 15

• Manufacturer Part Number: AT91M40400-25C
• Description: 16/32-bit Microcontroller, 2.7V to 3.6V Operating Range
• Manufacturer: ATMEL Corporation

Write Data Hold Time
During write cycles in both protocols, output data becomes
valid after the falling edge of the NWE signal and remains
valid after the rising edge of NWE, as illustrated in the fig-
ure below. The external NWE waveform (on the NWE pin)
is used to control the output data timing to guarantee this
operation.
It is therefore necessary to avoid excessive loading of the
NWE pins, which could delay the write signal too long and
cause a contention with a subsequent read cycle in stan-
dard protocol.
Figure 16. Data Hold Time
In early read protocol the data can remain valid longer than
in standard read protocol due to the additional wait cycle
which follows a write access.
Data output
ADDR
MCKI
NWE
Wait States
The EBI can automatically insert wait states. The different
types of wait states are listed below:
•
•
•
•
•
Standard Wait States
Each chip select can be programmed to insert one or more
wait states during an access on the corresponding device.
This is done by setting the WSE field in the corresponding
EBI_CSR. The number of cycles to insert is programmed in
the NWS field in the same register.
Below is the correspondence between the number of stan-
dard wait states programmed and the number of cycles
during which the NWE pulse is held low:
For each additional wait state programmed, an additional
cycle is added.
Figure 17. One Wait State access
Notes:
ADDR
Standard wait states
Data float wait states
External wait states
Chip select change wait states
Early Read wait states (as described in Read Protocols)
MCKI
NWE
NRD
NCS
0 wait states
1 wait state
1.
2.
Early Read Protocol
Standard Read Protocol
(1)
1 wait state access
(2)
1/2 cycle
1 cycle
AT91M40400
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