AT91M40400-25C ATMEL Corporation, AT91M40400-25C Datasheet - Page 50

• Manufacturer Part Number: AT91M40400-25C
• Description: 16/32-bit Microcontroller, 2.7V to 3.6V Operating Range
• Manufacturer: ATMEL Corporation

PIO: Parallel I/O Controller
The AT91M40400 has 32 programmable I/O lines. Six pins
on the AT91M40400 are dedicated as general purpose I/O
pins (P16, P17, P18, P19, P23 and P24). Other I/O lines
are multiplexed with an external signal of a peripheral to
optimize the use of available package pins (see Table 7).
The PIO controller also provides an internal interrupt signal
to the Advanced Interrupt Controller.
Multiplexed I/O Lines
Some I/O lines are multiplexed with an I/O signal of a
peripheral. After reset, the pin is generally controlled by the
PIO Controller and is in input mode. Table 7 indicates
which of these pins are not controlled by the PIO Controller
after reset.
When a peripheral signal is not used in an application, the
corresponding pin can be used as a parallel I/O. Each par-
allel I/O line is bi-directional, whether the peripheral defines
the signal as input or output. Figure 33 shows the multiplex-
ing of the peripheral signals with Parallel I/O signals.
If a pin is multiplexed between the PIO Controller and a
peripheral, the pin is controlled by the registers PIO_PER
(PIO Enable) and PIO_PDR (PIO Disable). The register
PIO_PSR (PIO Status) indicates whether the pin is con-
trolled by the corresponding peripheral or by the PIO Con-
troller.
If a pin is a general-purpose parallel I/O pin (not multi-
plexed with a peripheral), PIO_PER and PIO_PDR have no
effect and PIO_PSR returns 1 for the bits corresponding to
these pins.
When the PIO is selected, the peripheral input line is con-
nected to zero.
Output Selection
The user can enable each individual I/O signal as an output
wi th th e r eg is te r s P IO _O E R ( Ou tp ut E na bl e) a nd
PIO_ODR (Output Disable). The output status of the I/O
signals can be read in the register PIO_OSR (Output Sta-
tus). The direction defined has effect only if the pin is con-
figured to be controlled by the PIO Controller.
I/O Levels
Each pin can be configured to be driven high or low. The
level is defined in four different ways, according to the fol-
lowing conditions.
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AT91M40400
If a pin is controlled by the PIO Controller and is defined as
an output (see Output Selection above), the level is pro-
grammed using the registers PIO_SODR (Set Output Data)
and PIO_CODR (Clear Output Data). In this case, the pro-
grammed value can be read in PIO_ODSR (Output Data
Status).
If a pin is controlled by the PIO Controller and is not defined
as an output, the level is determined by the external circuit.
If a pin is not controlled by the PIO Controller, the state of
the pin is defined by the peripheral (see peripheral
datasheets).
In all cases, the level on the pin can be read in the register
PIO_PDSR (Pin Data Status).
Filters
Optional input glitch filtering is available on each pin and is
controlled by the registers PIO_IFER (Input Filter Enable)
and PIO_IFDR (Input Filter Disable). The input glitch filter-
ing can be selected whether the pin is used for its periph-
eral function or as a parallel I/O line. The register
PIO_IFSR (Input Filter Status) indicates whether or not the
filter is activated for each pin.
Interrupts
Each parallel I/O can be programmed to generate an inter-
rupt when a level change occurs. This is controlled by the
PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis-
able) registers which enable/disable the I/O interrupt by
setting/clearing the corresponding bit in the PIO_IMR.
When a change in level occurs, the corresponding bit in the
PIO_ISR (Interrupt Status) is set whether the pin is used as
a PIO or a peripheral and whether it is defined as input or
output. If the corresponding interrupt in PIO_IMR (Interrupt
Mask) is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically
cleared.
User Interface
Each individual I/O is associated with a bit position in the
Parallel I/O user interface registers. Each of these registers
are 32 bits wide. If a parallel I/O line is not defined, writing
to the corresponding bits has no effect. Undefined bits read
zero.