EMS6500 EM Microelectronic, EMS6500 Datasheet - Page 41

• Manufacturer Part Number: EMS6500
• Description: Microcontroller Development System 4-bit (Emmon), Simulators 4-bit
• Manufacturer: EM Microelectronic

Copyright  2003, EM Microelectronic-Marin SA
3.1.1. Instruction Register
3.1.2. Control Unit
3.1.3. Program Counter (PC)
3.1.4. Stack Pointer (SP)
3.1.5. Accumulator (Accu)
3.1.6. Status Register
3.1.7. Index Registers
3.1.8. Interrupts
indexes. The controllers have three program counters (PC) which means 2 possible
program levels when interrupts are enabled, or three program levels if the interrupts
are disabled.
This register stores the next instruction that will be executed.
This functional block generates the internal clock phases of the microcontroller,
controls the halt mode, the interrupt requests, decodes the instructions and sends
the control signals to the other blocks in microcontroller.
The program counter determines the ROM address of the next instruction to be
executed. The processor has a stack of three program counters (PC0 to PC2). The
current program counter is designated by the stack pointer (SP).
The stack pointer determines the current program counter (PC). At reset the SP is
reset to PC0.
The accumulator stores the 4 bit result of the ALU operations.
The status register is composed of three flags. The Z flag which is set to 1 if the
result of the last ALU operation equals zero. The Cy flag and the Cy_Int flag which
receive any addition, subtraction or shift carries. The Cy flag is used during normal
program execution and the Cy_Int flag is automatically selected during interrupt
handling thus conserving the state of the Cy flag during interrupt.
The index registers XH (index high, 3 bits) and XL (index low, 4 bits) are combined
to define a 7 bit offset in the IO (RAM / periphery) address space.
An interrupt can be generated by one or more peripherals. These signals are
combined with a logical OR gate to produce a single interrupt request to the
microcontroller core. The resulting interrupt request results in the microcontroller
executing a CALL 01 instruction and setting the INT flag. The RTI instruction signals
the end of the interrupt routine. It executes a return to the instruction which should
have been executed at the moment of the interruption ( as opposed to a RET
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Development System
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EM66xx
Binder 4.3-01/03 Rev. B/495