ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 12

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

ADSP-21367
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of TBD:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State, (pd) = pull-down
resistor, (pu) = pull-up resistor.
Table 3. Pin List
Name
ADDR
DATA
DAI _P
DPI _P
ACK
RD
WR
SDRAS
SDCAS
SDWE
SDCKE
SDA10
SDCLK0
31–0
23–0
14–1
20–1
Type
I/O with programmable
PUP
I/O with programmable
PUP
I/O with programma-
ble
I/O with programma-
ble
Input with programma-
ble PUP
I/O with programmable
PUP
Output with program-
mable PUP
Output with program-
mable PUP
Output with program-
mable PUP
Output with program-
mable PUP
Output with program-
mable PUP
Output with program-
mable PUP
I/O
2
3
1
1
PUP
PUP
1
1
1
1
1
1
1
State During
and After
Reset
Three-state
Three-state
Three-state
Three-state
Rev. PrA | Page 12 of 48 | November 2004
Description
External Address Bus.
External Data Bus.
Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any
input or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the Serial ports, Input data port, precision clock gen-
erators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins
have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can
be disabled in the DAI_PIN_PULLUP register.
Digital Peripheral Interface.
Memory Acknowledge. External devices can deassert ACK (low) to add wait states
to an external memory access. ACK is used by I/O devices, memory controllers, or
other peripherals to hold off completion of an external memory access.
External Port Read Enable. RD is asserted low whenever the processor reads 8-bit
or 16-bit data from an external memory device. When AD15–0 are flags, this pin
remains deasserted. RD has a 22.5 kΩ internal pull-up resistor.
External Port Write Enable. WR is asserted low whenever the processor writes 8-bit
or 16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR has a 22.5 kΩ internal pull-up resistor.
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin.
SDRAM column address select. Connect to SDRAM’s CAS pin.
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
SDRAM Clock Enable. Connect to SDRAM’s CKE pin.
SDRAM A10.
SDRAM Clock Configure.
Preliminary Technical Data