ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 32

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

ADSP-21367
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 26. SRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SRCSFS
SRCHFS
SRCTDD
SRCTDH
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold Before SCLK Rising Edge
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(SCLK)
(FS)
Rev. PrA | Page 32 of 48 | November 2004
Figure 21. SRC Serial Output Port Timing
t
SRCTDD
t
SRCCLKW
t
SRCTDH
SAMPLE EDGE
t
SRCSFS
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the drive
edge.
t
SRCHFS
t
SRCCLK
Min
4
5.5
2
Preliminary Technical Data
Max
7
Unit
ns
ns
ns
ns