ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 26

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

ADSP-21367
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 19. Serial Ports—External Clock
1
2
Table 20. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Referenced to the sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
1
1
2
2
1
1
2
2
1
1
2
2
2
1
2
2
2
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
Rev. PrA | Page 26 of 48 | November 2004
Serial port signals (SCLK, FS, data channel A,/data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Preliminary Technical Data
Min
2.5
2.5
2.5
2.5
24
48
2
2
Min
7
2.5
7
2.5
–1.0
–1.0
–1.0
0.5t
SCLK
– 2
Max
3
3
3
0.5t
Max
7
7
SCLK
+ 2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns