ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 16

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

ADSP-21367
ABSOLUTE MAXIMUM RATINGS
1
ESD SENSITIVITY
TIMING SPECIFICATIONS
The ADSP-21367’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor’s internal clock frequency and
external (CLKIN) clock frequency with the CLKCFG1–0 pins
(see
for the serial ports, divide down the internal clock, using the
programmable divider control of each port (DIVx for the serial
ports).
The ADSP-21367’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock (the
clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control
Table 6. ADSP-21367 CLKOUT and CCLK Clock
Generation Operation
Parameter
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage–0.5 V to V
Output Voltage Swing–0.5 V to V
Load Capacitance
Storage Temperature Range
Junction Temperature under Bias
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21367 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Timing
Requirements
CLKIN
CCLK
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 5 on page
1
14). To determine switching frequencies
Description
Input Clock
Core Clock
DDEXT
1
1
VDD
DDEXT
DDINT
DDEXT
)
1
)
1
)
1
1
Calculation
1/t
1/t
CK
CCLK
(Table
Rating
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+ 0.5 V
+ 0.5 V
200 pF
–65°C to +150°C
125°C
Rev. PrA | Page 16 of 48 | November 2004
6).
Table 7. Clock Periods
1
Figure 3
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP-
2136x SHARC Processor Programming Reference.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 34 on page 41
ence levels.
Timing
Requirements
t
t
t
t
t
t
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CK
CCLK
PCLK
SCLK
SDCLK
SPICLK
CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with
Preliminary Technical Data
under Test Conditions for voltage refer-
Description
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × t
Serial Port Clock Period = (t
SDRAM Clock Period = (TBD)
SPI Clock Period = (t
1
PCLK
) × SPIR
PCLK
) × SR
CCLK