ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 13

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

Preliminary Technical Data
Table 3. Pin List
Name
MS
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
MS2
FLAG[3]/TIMEX
P/MS3
TDI
TDO
TMS
TCK
TRST
EMU
CLK_CFG
BOOT_CFG
RESET
0–1
1–0
1–0
Type
I/O with programmable
PUP
I/O
I/O
I/O with
programmable
up (for MS mode)
I/O with
programmable
up (for MS mode)
Input with pull-up
Output
Input with pull-up
Input
Input with pull-up
Output with pull-up
Input
Input
Input
1
1
1
pull-
pull-
State During
and After
Reset
Rev. PrA | Page 13 of 48 | November 2004
Description
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the cor-
responding banks of external memory. Memory bank size must be defined in the
ADSP-21062’s system control register (SYSCON). The MS
address lines that change at the same time as the other address lines. When no
external memory access is occurring the MS3-0 lines are inactive; they are active
however when a conditional memory access instruction is executed, whether or not
the condition is true. In a multiprocessing system the MS
bus master.
FLAG0/Interrupt Request0.
FLAG1/Interrupt Request1.
FLAG2/Interrupt Request/Memory Select2.
FLAG3/Timer Expired/Memory Select3.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21367.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21367. TRST has a 22.5
kΩ internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21367 Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ
internal pull-up resistor.
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOTCFG pins must be valid before reset is asserted. See
the boot modes.
Processor Reset. Resets the ADSP-21367 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must be
asserted (low) at power-up.
3-0
3-0
Table 4
lines are decoded memory
lines are output by the
ADSP-21367
for a description of
Table 5