ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 22

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ADSP-21367

Manufacturer Part Number
ADSP-21367
Description
SHARC Processor
Manufacturer
Analog Devices
Datasheet

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ADSP-21367
Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specification provided below are
valid at the DAI_P20–1 pins.
Table 14. Timer Width Capture Timing
Pin to Pin Direct Routing (DAI and DPI)
For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 15. DAI Pin to Pin Routing
Parameter
Timing Requirement
t
Parameter
Timing Requirement
t
PWI
DPIO
Timer Pulse Width
Delay DAI Pin Input Valid to DAI Output Valid
(TIMER2-0)
DPI14-0
DAI_Pn
DPI_Pn
DAI_pm
DPI_Pm
Rev. PrA | Page 22 of 48 | November 2004
Figure 11. Timer Width Capture Timing
Figure 12. DAI Pin to Pin Direct Routing
Min
2 t
PCLK
t
t
PWI
DPIO
Min
1.5
Max
2(2
31
– 1) t
Preliminary Technical Data
PCLK
Max
10
Unit
ns
Unit
ns

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