16F84A Microchip Technology, 16F84A Datasheet - Page 13
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16F84A
Manufacturer Part Number
16F84A
Description
18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
Manufacturer
Microchip Technology
Datasheet
1.16F84A.pdf
(68 pages)
- Current page: 13 of 68
- Download datasheet (495Kb)
3.0
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™
(DS33023).
3.1
PORTA is a 5-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin.
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
EXAMPLE 3-1:
BCF
CLRF
BSF
MOVLW
MOVWF
1998 Microchip Technology Inc.
Note:
STATUS, RP0
PORTA
STATUS, RP0
0x0F
TRISA
I/O PORTS
PORTA and TRISA Registers
On a Power-on Reset, these pins are con-
figured as inputs and read as '0'.
Mid-Range
INITIALIZING PORTA
;
; Initialize PORTA by
; clearing output
; data latches
; Select Bank 1
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA4 as output
; TRISA<7:5> are always
; read as '0'.
Reference
Manual,
Preliminary
FIGURE 3-1:
Data
bus
WR
Port
WR
TRIS
RD PORT
Note: I/O pins have protection diodes to V
D
D
Data Latch
TRIS Latch
CK
CK
BLOCK DIAGRAM OF PINS
RA3:RA0
Q
Q
Q
Q
RD TRIS
PIC16F84A
Q
EN
D
TTL
input
buffer
DS35007A-page 13
DD
V
V
P
N
SS
DD
and V
SS
I/O pin
.
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