16F84A Microchip Technology, 16F84A Datasheet - Page 28

• Manufacturer Part Number: 16F84A
• Description: 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
• Manufacturer: Microchip Technology

PIC16F84A
6.7
On power-up (Figure 6-7, Figure 6-8, Figure 6-9 and
Figure 6-10) the time-out sequence is as follows: First
PWRT time-out is invoked after a POR has expired.
Then the OST is activated. The total time-out will vary
based
configuration bit status. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
TABLE 6-5
Since the time-outs occur from the POR reset pulse, if
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin
immediately (Figure 6-7). This is useful for testing
purposes or to synchronize more than one PIC16F84A
device when operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the reset conditions for some special
registers, while Table 6-4 lists the reset conditions for
all the registers.
TABLE 6-6
DS35007A-page 28
TO
Configuration
1
0
x
0
0
1
1
XT, HS, LP
Oscillator
RC
PD
on
Time-out Sequence and Power-down
Status Bits (TO/PD)
1
x
0
1
0
1
0
oscillator
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset (during normal operation)
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt
wake-up from SLEEP
1024T
TIME-OUT IN VARIOUS
SITUATIONS
STATUS BITS AND THEIR
SIGNIFICANCE
Enabled
72 ms +
PWRT
72 ms
OSC
Power-up
configuration
Condition
1024T
Disabled
PWRT
—
OSC
and
1024T
Wake-up
SLEEP
from
PWRTE
—
OSC
Preliminary
6.8
The PIC16F84A has 4 sources of interrupt:
• External interrupt RB0/INT pin
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
• Data EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable interrupts.
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
When an interrupt is responded to; the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs.
The latency is the same for both one and two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
FIGURE 6-11: INTERRUPT LOGIC
INTE
RBIF
RBIE
EEIE
INTF
EEIF
T0IE
T0IF
GIE
Note 1: Individual interrupt flag bits are set
Interrupts
regardless
corresponding mask bit or the GIE bit.
of
1998 Microchip Technology Inc.
the
status
Wake-up
(If in SLEEP mode)
Interrupt to CPU
of
their