16F84A Microchip Technology, 16F84A Datasheet - Page 29

• Manufacturer Part Number: 16F84A
• Description: 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
• Manufacturer: Microchip Technology

6.8.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 6.11) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
6.8.2
An overflow (FFh
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 4.0).
6.8.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 3.2).
EXAMPLE 6-1:
PUSH
ISR
POP
1998 Microchip Technology Inc.
Note 1: For a change on the I/O pin to be
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
MOVWF
SWAPF
SWAPF
INT INTERRUPT
TMR0 INTERRUPT
PORB INTERRUPT
on
recognized, the pulse width must be at
least T
the
CY
W_TEMP
STATUS, W
STATUS_TEMP
STATUS_TEMP, W
STATUS
W_TEMP, F
W_TEMP, W
SAVING STATUS AND W REGISTERS IN RAM
00h) in TMR0 will set flag bit T0IF
RB0/INT
wide.
pin,
the
; Copy W to TEMP register,
; Swap status to be saved into W
; Save status to STATUS_TEMP register
:
; Interrupt Service Routine
;
;
; Swap nibbles in STATUS_TEMP register
; and place result into W
; Move W into STATUS register
;
; Swap nibbles in W_TEMP and place result in W_TEMP
; Swap nibbles in W_TEMP and place result into W
should configure Bank as required
(sets bank to original state)
INTF
Preliminary
bit
6.8.4
At the completion of a data EEPROM write cycle, flag
bit EEIF (EECON1<4>) will be set. The interrupt can be
enabled/disabled by setting/clearing enable bit EEIE
(INTCON<6>) (Section 5.0).
6.9
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and STATUS
register). This is implemented in software.
Example 6-1 stores and restores the STATUS and W
register’s values. The User defined registers, W_TEMP
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
Example 6-1 does the following:
a)
b)
c)
d)
e)
Stores the W register.
Stores the STATUS register in STATUS_TEMP.
Executes the Interrupt Service Routine code.
Restores the STATUS (and bank select bit)
register.
Restores the W register.
DATA EEPROM INTERRUPT
Context Saving During Interrupts
PIC16F84A
DS35007A-page 29