16F84A Microchip Technology, 16F84A Datasheet - Page 31

• Manufacturer Part Number: 16F84A
• Description: 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
• Manufacturer: Microchip Technology

6.11
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
6.11.1
The Power-down mode is entered by executing the
SLEEP instruction.
If enabled, the Watchdog Timer is cleared (but keeps
running), the PD bit (STATUS<3>) is cleared, the TO bit
(STATUS<4>) is set, and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high, low,
or hi-impedance).
For the lowest current consumption in SLEEP mode,
place all I/O pins at either at V
external circuitry drawing current from the I/O pins, and
disable external clocks. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at V
contribution from on-chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (V
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
FIGURE 6-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Note
1998 Microchip Technology Inc.
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction
fetched
CLKOUT(4)
Instruction
executed
INT pin
1: XT, HS or LP oscillator mode assumed.
2: T
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
OSC1
Power-down Mode (SLEEP)
SLEEP
PC
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
OSC
(drawing not to scale) This delay will not be there for RC osc mode.
Q1 Q2 Q3 Q4
Inst(PC + 1)
SLEEP
PC+1
DD
DD
or V
or V
SS
Q1
Processor in
SLEEP
, with no
IHMC
SS
. The
PC+2
).
Preliminary
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
6.11.2
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
Peripherals cannot generate interrupts during SLEEP,
since no on-chip Q clocks are present.
The first event (MCLR reset) will cause a device reset.
The two latter events are considered a continuation of
program execution. The TO and PD bits can be used to
determine the cause of a device reset. The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up).
While the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
PC+2
External reset input on MCLR pin.
WDT Wake-up (if WDT was enabled).
Interrupt from RB0/INT pin, RB port change, or
data EEPROM write complete.
WAKE-UP FROM SLEEP
Interrupt Latency
Dummy cycle
(Note 2)
PC + 2
Q1 Q2 Q3 Q4
PIC16F84A
Inst(0004h)
Dummy cycle
0004h
DS35007A-page 31
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h