16F84A Microchip Technology, 16F84A Datasheet - Page 23

• Manufacturer Part Number: 16F84A
• Description: 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
• Manufacturer: Microchip Technology

6.2.3
For timing insensitive applications the RC device option
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) values, capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process
difference in lead frame capacitance between package
types also affects the oscillation frequency, especially
for low Cext values. The user needs to take into
account variation due to tolerance of the external
R and C components. Figure 6-4 shows how an R/C
combination is connected to the PIC16F84A.
FIGURE 6-4:
FIGURE 6-5:
Note 1: This is a separate oscillator from the
Cext
V
1998 Microchip Technology Inc.
Recommended values: 5 k
Rext
OSC1/
CLKIN
MCLR
SS
V
DD
V
DD
RC OSCILLATOR
RC oscillator of the CLKIN pin.
parameter
RC OSC
On-chip
OST/PWRT
Fosc/4
V
Module
RC OSCILLATOR MODE
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
detect
WDT
DD
(1)
rise
OST
PWRT
variation.
OSC1
OSC2/CLKOUT
Cext > 20pF
Time_Out
10-bit Ripple counter
WDT
Reset
10-bit Ripple counter
Power_on_Reset
External
Rext
Reset
SLEEP
Furthermore,
100 k
PIC16FXX
Internal
clock
Preliminary
the
6.3
The PIC16F84A differentiates between various kinds
of reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
Figure 6-5 shows a simplified block diagram of the
on-chip reset circuit. The MCLR reset path has a noise
filter to ignore small pulses. The electrical specifica-
tions state the pulse width requirements for the MCLR
pin.
Some registers are not affected in any reset condition;
their status is unknown on a POR reset and unchanged
in any other reset. Most other registers are reset to a
“reset state” on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
They are not affected by a WDT reset during SLEEP,
since this reset is viewed as the resumption of normal
operation.
Table 6-3 gives a description of reset conditions for the
program counter (PC) and the STATUS register.
Table 6-4 gives a full description of reset states for all
registers.
The TO and PD bits are set or cleared differently in dif-
ferent reset situations (Section 6.7). These bits are
used in software to determine the nature of the reset.
Enable PWRT
Enable OST
Reset
See Table 6-5
PIC16F84A
S
R
DS35007A-page 23
Q
Chip_Reset