16F84A Microchip Technology, 16F84A Datasheet - Page 20

• Manufacturer Part Number: 16F84A
• Description: 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
• Manufacturer: Microchip Technology

PIC16F84A
5.1
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 5-1:
5.2
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 5-1:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
TABLE 5-1
DS35007A-page 20
08h
09h
88h
89h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
Address
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF
BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
Reading the EEPROM Data Memory
Writing to the EEPROM Data Memory
used by data EEPROM.
Name
EEDATA
EEADR
EECON1
EECON2
STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W
STATUS, RP0
INTCON, GIE
EECON1, WREN ; Enable Write
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON, GIE
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
DATA EEPROM READ
DATA EEPROM WRITE
EEPROM data register
EEPROM address register
EEPROM control register 2
Bit 7
—
; Bank 0
;
; Address to read
; Bank 1
; EE Read
; Bank 0
; W = EEDATA
; Bank 1
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit
;
; Enable INTs.
Bit 6
—
begin write
Bit 5
—
EEIF
Bit 4
Preliminary
WRERR
Bit 3
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
5.3
Depending on the application, good programming prac-
tice may dictate that the value written to the Data
EEPROM should be verified (Example 5-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
Generally the EEPROM write failure will be a bit which
was written as a '0', but reads back as a '1' (due to
leakage off the bit).
EXAMPLE 5-1:
READ
;
; Is the value written (in W reg) and
;
;
WREN
Bit 2
BCF
:
:
MOVF
BSF
BSF
BCF
read (in EEDATA) the same?
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO
:
:
Write Verify
STATUS, RP0 ; Bank 0
EEDATA, W
STATUS, RP0 ; Bank 1
EECON1, RD
STATUS, RP0 ; Bank 0
WRITE_ERR
Bit 1
WR
WRITE VERIFY
Bit 0
RD
1998 Microchip Technology Inc.
; Any code can go here
;
; Must be in Bank 0
; YES, Read the
;
;
; Is difference 0?
; NO, Write error
; YES, Good write
; Continue program
value written
xxxx xxxx
xxxx xxxx
---0 x000
---- ----
Power-on
Value on
Reset
other resets
Value on all
uuuu uuuu
uuuu uuuu
---0 q000
---- ----