AD6641 Analog Devices, AD6641 Datasheet - Page 21

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

Addr.
(Hex)
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
Digital Controls
0x101
0x102
0x104
Fill control register
FIFO Config
Fill count
Parameter Name
OUTPUT_ADJUST
OUTPUT_PHASE
OUTPUT_DELAY
Input range
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
Bit 7
(MSB)
Output
clock
polarity:
1 =
inverted
0 =
normal
(default)
0
Reserved
(0.59 V to 0.80 V on
(20 kΩ pull-down)
00 = internal V
01 = import V
10 = export V
11= not used
VREF select:
VREF pin)
Bit 6
0
Fill
input
pin
disable
[7:4] = reserved
REF
REF
[7:4] = 0000
REF
Bit 5
0
Reserved
0
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Bit 4
LIFO
mode
0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0] = 0000000
Bit 3
LVDS
course
adjust:
0 =
3.5 mA
(default)
1 =
2.0 mA
Dump
reset
Input voltage range setting (V):
01 = continuous
FIFO fill mode:
1x = reserved
00 = single
11100 = 1.60
11101 = 1.58
11110 = 1.55
11111 = 1.52
00000 = 1.50
00001 = 1.47
00010 = 1.44
00011 = 1.42
00100 = 1.39
00101 = 1.36
00110 = 1.34
00111 = 1.31
01000 = 1.28
01001 = 1.26
01010 = 1.23
01100 = 1.18
01011= 1.20
Bit 2
Fill reset
Output clock delay:
0100 = reserved
0001 = −1/10
0010 = −2/10
0011 = −3/10
0101 = +5/10
0110 = +4/10
0111 = +3/10
1000 = +2/10
1001 = +1/10
0000 = 0
LVDS fine adjust:
001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
Bit 1
Reserved
Dump
Bit 0
(LSB)
Standby
after fill
Fill
Default
Value
(Hex)
0x00
0x03
0
0
0
0
0
0
0
0
0x7F
Default
Notes/
Comments
Shown as
fractional
value of
sampling
clock period
that is
subtracted or
added to
initial t
see Figure 3).
User Defined
Pattern 1 LSB.
User Defined
Pattern 1 MSB.
User Defined
Pattern 2 LSB.
User Defined
Pattern 2 MSB.
Number of
words to use
for fill or
dump.
AD6641
SKEW
,