ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 151

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.2 I
Subject to general operating conditions for V
f
Figure 104. Typical Application with I
Notes:
1. Data based on standard I
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
t
OSC
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
t
su(SDA)
t
t
su(STA)
su(STO)
t
t
h(SDA)
r(SDA)
h(STA)
SDA
SCL
r(SCL)
f(SDA)
f(SCL)
I
C
4
2
, and T
t
C BUS
f(SDA)
b
U
.com
2
C - Inter IC Control Interface
t
A
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
h(STA)
unless otherwise specified.
START
4.7k
t
w(SCKH)
t
r(SDA)
V
2
DD
C protocol requirement, not tested in production.
t
w(SCKL)
Parameter
4.7k
V
DD
t
su(SDA)
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t
r(SCK)
2
100
100
C Bus and Timing Diagram
t
h(SDA)
t
DD
f(SCK)
DD
,
SDAI
SCLI
and 0.7xV
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDAI and SCLI). The ST7 I
requirements of the Standard I
protocol described in the following table.
ST72XXX
Standard mode I
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
DD
3)
.
1)
ST72260G, ST72262G, ST72264G
Max
4)
1000
300
400
2
1)
C
t
su(STA)
20+0.1C
20+0.1C
t
su(STO)
Min
100
0
Fast mode I
1.3
0.6
0.6
0.6
0.6
1.3
2
2)
C interface meets the
1)
t
w(STO:STA)
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STOP
2
b
b
C communication
REPEATED START
Max
900
300
300
400
2
C
3)
1)
START
151/171
Unit
ms
pF
ns
ns
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