ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 33
ST72F264G
Manufacturer Part Number
ST72F264G
Description
(ST72F260G - ST72F264G) 8-BIT MCU
Manufacturer
ST Microelectronics
Datasheet
1.ST72F264G.pdf
(171 pages)
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DataSheet
8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, three main
power saving modes are implemented in the ST7
(see
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 21. Power Saving Mode Transitions
4
Figure
U
.com
21).
SLOW WAIT
POWER CONSUMPTION
SLOW
HALT
WAIT
RUN
Low
High
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CPU
).
8.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
– To adapt the internal clock frequency (f
SLOW mode is controlled by three bits in the
MISR1 register: the SMS bit which enables or dis-
ables Slow mode and two CPx bits which select
the internal slow frequency (f
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 22. SLOW Mode Clock Transitions
internal clock in the device,
the available supply voltage.
CP1:0
SMS
f
CPU
f
OSC2
ST72260G, ST72262G, ST72264G
f
FREQUENCY
OSC2
00
NEW SLOW
REQUEST
/2
01
CPU
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f
OSC2
NORMAL RUN MODE
).
/4
REQUEST
CPU
f
OSC2
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