ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 62

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ST72F264G

Manufacturer Part Number
ST72F264G
Description
(ST72F260G - ST72F264G) 8-BIT MCU
Manufacturer
ST Microelectronics
Datasheet

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DataSheet
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OC i HR reg-
2. If the OC i E bit is not set, the OCMP i pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 42. Output Compare Block Diagram
62/171
16-bit
ister, the output compare function is inhibited
until the OC i LR register is also written.
general I/O port and the OLVL i bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMP i are set while the counter value equals
the OC i R register value (see
63). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
external clock mode, OCF i and OCMP i are set
while the counter value equals the OC i R regis-
ter value plus 1 (see
for generating external events on the OCMP i
pins even if the input capture mode is also
used.
OLV i bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
4
OUTPUT COMPARE
U
16-bit
.com
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure 44 on page
CPU
i
R register and the
CPU
Figure 43 on page
/4, f
/2, OCF i and
OC1E
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CPU
OCIE
OC2E
OCF1
/8 or in
63).
FOLV2 FOLV1
Forced Compare Output capability
When the FOLV i bit is set by software, the OLVL i
bit is copied to the OCMP i pin. The OLV i bit has to
be toggled in order to toggle the OCMP i pin when
it is enabled (OC i E bit=1). The OCF i bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVL i bits have no effect in both one pulse
mode and PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
Latch
Latch
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1
2
OCMP1
OCMP2
Pin
Pin
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