ST14C02C ST Microelectronics, ST14C02C Datasheet - Page 6

• Manufacturer Part Number: ST14C02C
• Description: Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM
• Manufacturer: ST Microelectronics

ST14C02C
Table 5. Operating Modes
Note: 1. X =
byte Write mode may modify data bytes in an ad-
jacent row. (Each row is 8 bytes long). However,
the Multibyte Write can properly write up to eight
consecutive bytes only if the first address is the
first address of the row (the seven following bytes
thereby being written to the seven following bytes
of this same row).
When not connected, the MODE pin is internally
pulled to “1” and the multibyte write option is se-
lected.
Page Write
For the Page Write mode, the MODE pin must be
held at V
mode allows up to eight bytes to be written in a sin-
gle write cycle, provided that they are all located in
the same row. That is, the five most significant
memory address bits (A7-A3) must be the same.
The master sends between one and eight bytes of
data, each of which are acknowledged by the
memory. After each byte is transferred, the inter-
nal byte address counter is incremented (this han-
dles the three least significant address bits). Care
must be taken to avoid address counter ‘roll-over’,
as this could result in data being overwritten.
The transfer is terminated by the master generat-
ing a STOP condition. For any write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All in-
puts are disabled until the completion of this cycle
and the memory will not respond to any request.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t
typical time is shorter. To make use of this, an ACK
polling sequence can be used by the master.
6/12
Current Address Read
Random Address Read
Sequential Read
Byte Write
Multibyte Write
Page Write
IL
V
(as shown in Table 5). The Page Write
IH
Mode
or V
IL
w
.
) is indicated in Table 8, but the
RW bit
‘1’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
MODE
V
V
X
X
X
X
X
IH
IL
1
The sequence, as shown in Figure 7, is as follows:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
– Step 2: if the memory is busy with the internal
Read Operations
Read operations are independent of the state of
the MODE pin. On delivery, the memory content is
set at all “1’s” (FFh).
Current Address Read
The memory has an internal byte address counter.
Each time a byte is read, this counter is increment-
ed. For the Current Address Read mode, following
a START condition, the master sends a device se-
lect with the RW bit set to ‘1’. The memory device
acknowledges this, and outputs the byte ad-
dressed by the internal byte address counter, as
shown in Figure 9. The counter is then increment-
ed. The master must not acknowledge the byte
output, and terminates the transfer with a STOP
condition.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 6.
This is followed by another START condition from
the master and the device select is repeated with
the RW bit set to ‘1’. The memory device acknowl-
edges this, and outputs the byte addressed. The
master must not acknowledge the byte output, and
terminates the transfer with a STOP condition.
followed by a device select byte (first byte of the
new instruction).
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an ACK, indicating that the memory is
ready to receive the second part of the next in-
struction (the first byte of this instruction having
been sent during Step 1).
Bytes
1
1
1
4
8
1
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Mode
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
Initial Sequence