HM-6518 Intersil Corporation, HM-6518 Datasheet - Page 6

• Manufacturer Part Number: HM-6518
• Description: 1024 x 1 CMOS RAM
• Manufacturer: Intersil Corporation

NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
In the HM-6518/883 read cycle the address information is
latched into the on chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time require-
ments must be met. After the required hold time the
addresses may change state without affecting device oper-
ation. In order for the output to be read S1, S2 and E must
Timing Waveforms
REFERENCE
TIME
-1
0
1
2
3
4
5
REFERENCE
TIME
S1,
S2
W
Q
A
D
E
E
H
H
L
L
HIGH Z
S1
(8) TAVEL
H
X
H
X
L
L
L
TEHEL (7)
-1
INPUTS
W
H
H
H
H
H
X
X
0
VALID
TELAX
(9)
FIGURE 2. WRITE CYCLE
A
X
V
X
X
X
X
V
HM-6518/883
1
TRUTH TABLE
6-90
TELWH (15)
D
X
X
X
X
X
X
X
be low, W must be high. When E goes high the output data
is latched into an on chip register. Taking either or both S1
or S2 high, forces the output buffer to a high impedance
state. The output data may be re-enabled at any time by
taking S1 and S2 low. On the falling edge of E the data will
be unlatched.
TELEH (6)
TSLWH (14)
TWLWH (16)
TWLSH (12)
TWLEH (13)
TDVWH (10)
VALID DATA
OUTPUTS
TELEL (17)
Q
Z
Z
X
V
V
Z
Z
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Output Latched
Device Disabled, Prepare for Next Cycle
(Same as -1)
Cycle Ends, Next Cycle Begins
(Same as 0)
2
3
TWHDX (11)
(8) TAVEL
TEHEL (7)
FUNCTION
4
5
NEXT