ACS-I1024-CPGA Photon Vision Systems, Inc., ACS-I1024-CPGA Datasheet - Page 10

• Manufacturer Part Number: ACS-I1024-CPGA
• Description: High Performance Area CMOS Image Sensor
• Manufacturer: Photon Vision Systems, Inc.

When the device is in MASTER mode, the on-chip state machine uses the information in the setup registers to control the
imager. These registers are 12 bits wide. The register data can be accessed via the bi-directional REG_DATA 12 bit wide
parallel bus, pins 1-7 and 99-103. These are accessed via a 5 bit address bus ADD, pins 77-81. The Input signals N_CS (pin
54) and N_WR (pin 55) are used to control the reading of, or writing to, of the setup registers. See SETUP REGISTER
ACCESS TIMING diagrams, below.
Region of Interest Registers:
The device has the ability to control 2 regions of interest simultaneously. This allows for faster sub frame readout. The ROI
Registers must contain a valid non-zero value for that ROI to operate. Note that at least one of the ROI’s must be setup in
order to scan video. The ROIs can overlap, but note that the pixels read in the first ROI are valid in the overlap region. When
the second ROI is read, the pixels sharing the same rows as that of the first ROI will not be valid.
The SETUP registers are as follows;
REGISTER
ADDRESS
SETUP REGISTERS
15-1F
(Hex)
10
11
12
13
14
A
B
D
C
E
0
1
2
3
4
5
6
7
8
9
F
TRANSFER
NAME
ROI 0 Row Start
ROI 0 Row Stop
ROI 0 Col. Start
ROI 0 Col. Stop
ROI 1 Row Start
ROI 1 Row Stop
ROI 1 Col. Start
ROI 1 Col. Stop
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FFS HOLDOFF
CONTROL 0
CONTROL 1
ROLLING
HOLDOFF
Reserved
Product DATASHEET ACS-I XXX Rev. 10/31/00 Subject to change without notice. Page 10 of 26
DESCRIPTION
Row Address of pixel for ROI 0 to Start – must be less than REG. 1.
Row Address of pixel for ROI 0 to Stop – Must be greater than
Column Address of pixel for ROI 0 to Stop – Must be greater than
Row Address of pixel for ROI 1 to Start – must be less than REG. 5.
Row Address of pixel for ROI 1 to Stop – Must be greater than
Column Address of pixel for ROI 1 to Stop – Must be greater than
Transfer Control Register. The charge is transferred from the pixel
Control Register 0 – See Register 0 bit description, below.
Control Register 1 – See Register 1 bit description, below.
Do not write to these Registers.
REG. 0.
Column Address of pixel for ROI 0 to Start – must be less than
REG. 3.
REG. 2.
REG. 4.
Column Address of pixel for ROI 1 to Start – must be less than
REG. 7.
REG. 6.
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Full Frame Shutter Mode Holdoff Control Register. This register
contains the ‘hold off’ time from the start of the state machine logic
until the pixel site is allowed to accumulate charge. The pixels are
held in reset for this time period. The register default is 0 for full
frame integration.
to the storage site when the state machine logic reaches the value of
this register. If the STOP bit (bit 11) in Control Register 0 is set
high, a new frame cycle will then begin.
Rolling Shutter mode Holdoff Control Register, controls exposure
time in rolling shutter mode. This register determines the number of
rows back from the current row being read to reset and put back into
integration that row. Units are in rows.

Photon Vision Systems, Inc. 1999, 2000
PRELIMINARY
DEFAULT
VALUE
0
1023
0
1023
0
0
0
0
0
0
0
0
0
0
0
0
0
0
See Below
See Below
0
0