ACS-I1024-CPGA Photon Vision Systems, Inc., ACS-I1024-CPGA Datasheet - Page 7

• Manufacturer Part Number: ACS-I1024-CPGA
• Description: High Performance Area CMOS Image Sensor
• Manufacturer: Photon Vision Systems, Inc.

44
45
46
47
48
49
50
51
52
53
54
CRST
RESET
PAUSE
MASTER
GAIN1
GAIN0
OFFSET1
OFFSET0
DIG_PAD_GND
DIG_PAD_PWR
_____
N_CS
Product DATASHEET ACS-I XXX Rev. 10/31/00 Subject to change without notice. Page 7 of 26
Digital Input
TX CRST
0
1
X
X
Digital Input
Digital Input
0 - Transfer and read
1 - Transfer and pause
Digital Input
0 - SLAVE Mode
1 - MASTER Mode
Digital Input
GAIN0, 1 OFFSET0, 1
Digital Input
See table, pin 48.
Digital Input
See table, pin 48.
Digital Input
See table, pin 48.
Digital Pad Power
Ground
Digital Pad Power
5.0 VDC
Digital Input
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X - M1
X - M2
0 - M3
1 - M4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1 - S1
0 - S2
1 - S3
0 - S4
1 - S5
0 - S6
1 - S7
0 - S8
1 - S9
0 - S10
1 - S11
0 - S12
1 - S13
0 - S14
1 - S15
0 - S16

Photon Vision Systems, Inc. 1999, 2000
Exposure Control LSB, used in conjunction with pin 57. If in SLAVE mode, input
Exposure control. This is a global (all pixels) function. Note that TX and CRST are
global for all pixels at once.
M1 - Transfer accumulated charge from pixel to Storage site.
M2 - Storage Site retains current charge
M3 - Reset pixels
M4 - Accumulate charge at pixel - Begin Integrating
RESET Command bit. Forces master reset of state machine to default values.
PAUSE Control bit. If in SLAVE mode, input PAUSE.
When bit is on, the device will halt after transferring the charge to the hold site. This
will prevent the readout cycle from beginning until the bit is cleared. Note that in
MASTER mode, both the SETUP register control bit for PAUSE and this PAUSE
signal must both be OFF for a read cycle to begin.
MASTER/SLAVE Mode select. When ON, device is in MASTER mode. When OFF,
device is in SLAVE Mode. When in MASTER mode, those signals indicated with the
'M/S' symbol indicate that the function of these signals is depends on the selected
Mode. Typically when the device is in MASTER mode, the 'M/S' signals like the row
and column address buses output the currently accessed pixel. When in SLAVE mode,
the 'M/S' signals are used to externally access these buses for random access.
GAIN and OFFSET control. Works in conjunction with pins 49-51. If in SLAVE
mode input desired Gain and offset from table below. Default is 1X gain and no offset.
S1 -
S2 -
S3 -
S4 -
S5 -
S6 -
S7 -
S8 -
S9 -
S10 -
S11 -
S12 -
S13 –
S14 -
S15 -
S16 -
GAIN and OFFSET control. Works in conjunction with pins 48, 50, and 51. If in
SLAVE mode input desired Gain and offset from table – see pin 48.
GAIN and OFFSET control. Works in conjunction with pins 48, 49, and 51. If in
SLAVE mode input desired Gain and offset from table – see pin 48.
GAIN and OFFSET control. Works in conjunction with pins 49-50. If in SLAVE
mode input desired Gain and offset from table – see pin 48.
Power ground for Digital Pad circuits except video DATA Pads, see pins 83-98.
Connected on-chip with pins 9, 75 and 76.
Power in for Digital Pad circuits except video DATA Pads, see pins 83-98.
Connected on-chip with pins 8, 53, 72, 73, and 74.
Controls direction of REG_DATA lines, pins 99-100 and pins 1-7, by reading or
writing to setup registers. Works in conjunction with pin 55. See SETUP REGISTER
TIMING diagrams for details.
Verbal description - Register WRITE cycle:
With pin 54 high, set pin 54 low and input register address on the ADD lines, pins 77-
81 and also input register data to REG_DATA lines, pins 99-100 and 1-7. Pulse pin 54
low for one clock cycle to write the data to the setup register.
Verbal description - Register READ cycle:
With pin 54 high, set pin 55 high and input register address on the ADD lines, pins 77-
81. Set pin 54 low to output register data to REG_DATA lines, pins 99-100 and 1-7.
PRELIMINARY
GAIN SETTING
1.00
1.33
2.00
4.00
4.00
4.00
4.00
2.00
2.00
1.33
NA
NA
NA
NA
NA
NA
OFFSET SETTING (Volts)
0.00
0.30
0.60
0.90
0.30
-0.30
-0.90
0.00
-0.60
-0.30