ACS-I1024-CPGA Photon Vision Systems, Inc., ACS-I1024-CPGA Datasheet - Page 5

• Manufacturer Part Number: ACS-I1024-CPGA
• Description: High Performance Area CMOS Image Sensor
• Manufacturer: Photon Vision Systems, Inc.

Bond
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
Device Bond-out
REG_DATA_5
REG_DATA_6
REG_DATA_7
REG_DATA_8
REG_DATA_9
REG_DATA_10
REG_DATA_11
DIG_PAD_PWR
DIG_PAD_GND
C_DATA_0
M/S
C_DATA_1
M/S
C_DATA_2
M/S
C_DATA_3
M/S
C_DATA_4
M/S
C_DATA_5
M/S
C_DATA_6
M/S
C_DATA_7
M/S
C_DATA_8
M/S
C_DATA_9
M/S
C_DATA_10
M/S
C_DATA_11
M/S
R_DATA_0
M/S
R_DATA_1
M/S
Name
Product DATASHEET ACS-I XXX Rev. 10/31/00 Subject to change without notice. Page 5 of 26
Bi-directional I/O
See pins 54, 55
Bi-directional I/O
See pins 54, 55
Bi-directional I/O
See pins 54, 55
Bi-directional I/O
See pins 54, 55
Bi-directional I/O
See pins 54, 55
Bi-directional I/O
See pins 54, 55
Bi-directional I/O
See pins 54, 55
Digital Pad Power
5.0 VDC
Digital Pad Power
Ground
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Bi-directional I/O
Digital In - SLAVE
Digital Out - MAST
Signal Type

Photon Vision Systems, Inc. 1999, 2000
Setup Register data bit 5.
See Register setup table for more information
Setup Register data bit 6.
See Register setup table for more information
Setup Register data bit 7.
See Register setup table for more information
Setup Register data bit 8.
See Register setup table for more information
Setup Register data bit 9.
See Register setup table for more information
Setup Register data bit 10.
See Register setup table for more information
Setup Register data bit 11, MSB.
See Register setup table for more information
Power in for Digital Pad circuits except video DATA Pads, see pins 83-98.
Connected on-chip with pins 53, 72, 73, and 74.
Power ground for Digital Pad circuits except video DATA Pads, see pins 83-98.
Connected on-chip with pins 52, 75, and 76.
Column address LSB BIT 0 - If in SLAVE mode, input column address for random
access. If in MASTER mode, output for currently addressed pixel. Pin must be
connected whenever in SLAVE mode, do not float.
Column address BIT 1 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address BIT 2 - If in SLAVE mode, input column Pin must be connected
whenever in SLAVE mode, do not float. address for random access. If in MASTER
mode, output for currently addressed pixel.
Column address BIT 3 - If in SLAVE mode, input column Pin must be connected
whenever in SLAVE mode, do not float. address for random access. If in MASTER
mode, output for currently addressed pixel.
Column address BIT 4 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address BIT 5 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address BIT 6 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address BIT 7 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address BIT 8 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address BIT 9 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address BIT 10 - If in SLAVE mode, input column address for random access.
If in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Column address MSB BIT 11 - If in SLAVE mode, input column address for random
access. If in MASTER mode, output for currently addressed pixel. Pin must be
connected whenever in SLAVE mode, do not float.
Row address LSB BIT 0 - If in SLAVE mode, input Row address for random access. If
in MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
Row address BIT 1 - If in SLAVE mode, input Row address for random access. If in
MASTER mode, output for currently addressed pixel. Pin must be connected
whenever in SLAVE mode, do not float.
PRELIMINARY
Description