ACS-I1024-CPGA Photon Vision Systems, Inc., ACS-I1024-CPGA Datasheet - Page 14

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ACS-I1024-CPGA

Manufacturer Part Number
ACS-I1024-CPGA
Description
High Performance Area CMOS Image Sensor
Manufacturer
Photon Vision Systems, Inc.
Datasheet
VIDEO OUT TIMING DIAGRAMS:
The following illustrates video output timing. Both the Analog out and the Digital out are shown. Note that at the
end of every row read, whether within an ROI or entire frame, there is a 40 clock (CLK1X) delay where the video
data is not valid. At 40MHz CLK_IN_2X, this corresponds to a 2 microsecond delay. The CLK1X signal is the pixel
out clock.
Note that the video data, whether digital or analog, lags the column and row address by 5 CLK_IN_2X cycles. In
other words, when the sixth pixel row and column address appears on the R_DATA and C_DATA buses (SLAVE or
MASTER mode), the first pixels data is output on the video ports.
FRAME TIMING DIAGRAM
Diagram shows video output for a 3 by 3 ROI, again with a 40MHz CLK2X.
VIDEO ROW DATA TIMING DIAGRAM.
Diagram shows a few pixels selected. Times shown are based on input CLK2X frequency of 40MHz.
Product DATASHEET ACS-I XXX Rev. 10/31/00 Subject to change without notice. Page 14 of 26
Photon Vision Systems, Inc. 1999, 2000
PRELIMINARY

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