ACS-I1024-CPGA Photon Vision Systems, Inc., ACS-I1024-CPGA Datasheet - Page 11

• Manufacturer Part Number: ACS-I1024-CPGA
• Description: High Performance Area CMOS Image Sensor
• Manufacturer: Photon Vision Systems, Inc.

CONTROL REGISTERS:
CONTROL REGISTER 0 and 1 are broken into separate control bits, as described below. Note that some of these bits have a
corresponding I/O pin. The I/O pin is used for the described function whenever the device is in SLAVE mode, otherwise, the I/O
pin is ignored in MASTER mode. See the bond out table above for more information.
CONTROL REGISTER BIT DESCRIPTIONS
CONT
ROL
REGIS
TER
0
0
0
0
0
0
0
0
0
0
0
0
BIT
#
10
11
0
1
2
3
5
6
4
7
8
9
Name
F1
F0
G1
G0
SYNC
TM
CS2
CS1
CS2 CS1
CS0
CS0 - 0 250us
CS0 - 1 1ms
CDS1
CDS1 CDS0
CDS0
!STOP
0
0
1
1
Product DATASHEET ACS-I XXX Rev. 10/31/00 Subject to change without notice. Page 11 of 26
0
0
1
1
0 – SR1
1 – SR2
0 – SR3
1 – SR4
0 – RM0
1 – RM1
0 – RM2
1 – RM3
Description
Offset select bit 1. Works in conjunction with bits 1, 2, and 3 below. See
bond out description for pin 50 for more information. This bit only
works in MASTER mode.
Offset select bit 0. Works in conjunction with bits 0, 2, and 3. See bond
out description for pin 51 for more information. This bit only works in
MASTER mode.
Gain select bit 1. Works in conjunction with bits 0, 1, and 3. See bond
out description for pin 48 for more information. This bit only works in
MASTER mode.
Gain select bit 0. Works in conjunction with bits 0, 1 and 2 above. See
bond out description for pin 49 for more information. This bit only
works in MASTER mode.
Same as I/O pin 56, used only in MASTER mode. See BOND OUT
table above for more information.
Transfer Mode bit select – Reserved for future use
Clocks select bit 2. Works in conjunction with CS1, see bit 7 below.
Clock Select bit 1, in conjunction with CS2, selects the clock rate for
pixel read out. Frequency is based on 40 MHz Master clock. Frequency
will vary with varying Master clock.
SR1 is 20Mhz. (Master clock/2)
SR2 is 10Mhz. (Master clock/4)
SR3 is 5Mhz. (Master clock/8)
SR4 is 2.5Mhz. (Master clock/16)
Clock Select bit 0, selects time base for exposure control. Periods based
on 40MHz Master input clock. Period will vary with varying Master
clock.
CS0 set to 0 selects 250us clock period (4 kHz). Max. integration is 1
second.
CS0 set to 1 selects 1ms clock period (1 kHz). Max. integration is 4
seconds.
Same as I/O pin 38, used only in MASTER mode. See BOND OUT
table above for more information. Works in conjunction with bits 5 and
10.
RM0 – unsupported mode
RM1 – Rolling shutter, destructive readout
RM2 – Snap Shot shutter, non-destructive readout
RM3 – Snap Shot shutter, destructive read
Same as I/O pin 39, used only in MASTER mode. See BOND OUT
table above for more information. Works in conjunction with bits 5 and
9.
STOP bit, this is a true low bit. When this bit is set to 0, the state
machine logic will halt the device at the end of the next read cycle. The
next cycle will occur when SYNC pin 56 is asserted (Asynchronous
capture) When set to 1, the state machine allows continuos cycles.

Photon Vision Systems, Inc. 1999, 2000
PRELIMINARY
Default
0
0
1
1
0
0
0
0
0
1
0
0