ACS-I1024-CPGA Photon Vision Systems, Inc., ACS-I1024-CPGA Datasheet - Page 8

• Manufacturer Part Number: ACS-I1024-CPGA
• Description: High Performance Area CMOS Image Sensor
• Manufacturer: Photon Vision Systems, Inc.

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______
N_WR
SYNC
TX
COL_LOAD
ROW_LOAD
GB_ANA_GND
ANA_GND2
ANA_GND1
ANA_PAD_GND
GB_ANA_PWR
ANA_PAD_PWR
PIX_AMP_ANA_P
WR
ANA_PWR1
ANA_PWR2
ANALOG_OUT
BIAS_PAD_EXT
ANALOG_IN
DIG_PAD_PWR
DIG_PWR
DIG_GB_PWR
DIG_PAD_GND
DIG_GND
ADD0
ADD1
ADD2
Product DATASHEET ACS-I XXX Rev. 10/31/00 Subject to change without notice. Page 8 of 26
Digital Input
Digital Input
Digital Input
See table, pin 44
Digital Input
SLAVE only
Digital Input
SLAVE only
Guard Band analog
Ground.
Analog Circuits 2
Ground
Analog Circuits 1
Ground
Analog Pad
Ground
Guard Band analog
POWER 5.0 VDC
Analog Pad POWER
5.0 VDC
Analog Power
5.0 Volts
Analog Circuits 1
POWER 5.0 VDC
Analog Circuits 2
POWER 5.0 VDC
Analog Video Out
Analog pixel Bias
Analog input,
Range 0.9-3.2 VDC
Digital Pad Power
5.0 VDC
Digital Circuits Power
5.0 VDC
Digital Guard Band
Power 5.0 VDC
Digital Pad Ground
Digital Ground
Digital Input
Setup Register Address
Bit 0 - LSB.
Digital Input
Setup Register Address
Bit 1.
Digital Input
Setup Register Address
Bit 2.

Photon Vision Systems, Inc. 1999, 2000
writing to setup registers. Works in conjunction with pin 54. See SETUP REGISTER
TIMING diagrams for details. Do not change the state of this pin whenever pin 54 is
low, or register data corruption and/or unpredictable operation or device damage may
result.
External Input that controls the exposure state machine when the stop bit of the control
register is set to zero. Rising edge of SYNC starts the exposure control state machine.
This allows external synchronization of the imager. Otherwise if STOP bit in the
control register is high, the imager free runs asynchronously.
Exposure Control MSB, used in conjunction with pin 44. If in SLAVE mode, input
Exposure control. This is a global (all pixels) function.
Load Column Address that is loaded onto C_DATA bus (pins 10-21) into imager.
Only Works in SLAVE mode.
Load Row Address that is loaded onto the R_DATA bus (pins 22-33) into imager.
Only works in SLAVE mode.
Ground input for Analog guard band.
Use with pin 64 and must be connected.
Ground input for the A/D.
Use with pin 68 and must be connected.
Ground input for the A/D.
Use with pin 67 and must be connected.
Ground input for analog pads.
Use with pin 65 and must be connected.
Power in for Analog Guard Band.
Use with pin 60 and must be connected.
Power in for analog pads.
Use with pin 63 and must be connected.
Power to Column amplifier
Power in for the A/D.
Use with Pin 62 and must be connected.
Power in for the A/D.
Use with pin 61 and must be connected.
Video output - analog. Do not Connect if using Digital output. See Electrical
Parameters for maximum load. Referenced to pin 61.
Tie a 10-30pF capacitor from this pin to analog ground, pin 63.
Referenced to pin 62. Use this pin to input an external analog signal for referencing
the A/D and/or calibration. Note that the last pixel of each frame read is the converted
value of this reference, not the value of the pixel, when Control Reg. 1 bit 1 is set high.
Power in for Digital Pad circuits except video DATA Pads, see pins 83-98.
Connected on-chip with pins 8, 53, 73, and 74.
Power in for Digital circuits except video DATA Pads, see pins 83-98.
Connected on-chip with pins 8, 53, 72, and 74.
Power in for Digital Guard Band.
Connected on-chip with pins 8, 53, 72, and 73.
Power in for Digital Pad circuits except video DATA Pads, see pins 83-98.
Connected on-chip with pins 9, 52, and 76.
Ground input for Digital circuits. See also pin 75.
Connected on-chip with pins 9, 52, and 75.
Setup register address bit 0 - LSB. Address bus for access to the SETUP REGISTERS.
See pins 54-55, 99-103, and 1-7.
Setup register address bit 1. Address bus for access to the SETUP REGISTERS. See
pins 54-55, 99-103, and 1-7.
Setup register address bit 2. Address bus for access to the SETUP REGISTERS. See
pins 54-55, 99-103, and 1-7.
Controls direction of REG_DATA lines, pins 99-100 and pins 1-7, by reading or
PRELIMINARY