74HCT7030D,112 NXP Semiconductors, 74HCT7030D,112 Datasheet - Page 10

• Manufacturer Part Number: 74HCT7030D,112
• Description: IC 9X64 FIFO REGISTER 3ST 28SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT7030D,112

• Function: Asynchronous, Synchronous
• Memory Size: 576 (9 x 64)
• Data Rate: 33MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Logic Family: HCT
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 9
• Number Of Inputs: 9
• Number Of Outputs: 9
• High Level Output Current: -6mA
• Low Level Output Current: 6mA
• Propagation Delay Time: 117ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 36(Typ)MHz
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 50uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-2900-5; 933798900112

Philips Semiconductors
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
Output capability: standard
I
Note to HCT types
The value of additional quiescent supply current ( I
To determine I
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
December 1990
CC
INPUT
OE
SI
D
MR
SO
SYMBOL
t
t
t
t
t
t
t
t
t
t
PHL
PHL
PHL
PHL
PHL
PLH
PLH
PZH
PHZ
THL
9-bit x 64-word FIFO register; 3-state
n
category: LSI
/ t
/ t
/ t
/ t
/ t
/ t
/ t
/ t
TLH
PLH
PLH
PLH
PLH
PLH
PZL
PLZ
UNIT LOAD COEFFICIENT
1.00
1.50
0.75
1.50
1.50
r
PARAMETER
propagation delay
propagation delay
propagation delay
propagation delay
propagation delay
propagation delay/ripple
propagation delay/
3-state output enable
3-state output disable
output transition time
= t
MR to DIR, DOR
SI to DIR
SO to DOR
SO to Q
DOR to Q
through delay
SI to DOR
bubble-up delay
SO to DIR
OE to Q
OE to Q
CC
f
= 6 ns; C
per input, multiply this value by the unit load coefficient shown in the table below.
n
n
n
n
L
= 50 pF
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
min. typ. max. min. max. min.
30
29
39
46
7
0.9
1.2
20
19
7
25
CC
51
49
67
78
12
1.6
2.0
35
35
15
) for a unit load of 1 is given in the family specifications.
10
T
74HCT
amb
40 to 85
( C)
53
61
84
98
15
2.0
2.5
44
44
19
40 to 125
63
74
101
117
18
2.4
3.0
53
53
22
max.
.
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
s
s
74HC/HCT7030
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
V
TEST CONDITIONS
(V)
CC
Product specification
WAVEFORMS
Fig.8
Fig.6
Fig.9
Fig.14
Fig.10
Fig.10
Fig.7
Fig.16
Fig.16
Fig.14