74HCT7030D,112 NXP Semiconductors, 74HCT7030D,112 Datasheet - Page 13

• Manufacturer Part Number: 74HCT7030D,112
• Description: IC 9X64 FIFO REGISTER 3ST 28SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT7030D,112

• Function: Asynchronous, Synchronous
• Memory Size: 576 (9 x 64)
• Data Rate: 33MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Logic Family: HCT
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 9
• Number Of Inputs: 9
• Number Of Outputs: 9
• High Level Output Current: -6mA
• Low Level Output Current: 6mA
• Propagation Delay Time: 117ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 36(Typ)MHz
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 50uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-2900-5; 933798900112

Philips Semiconductors
Master reset applied with FIFO full
Shifting out sequence; FIFO full to FIFO empty
December 1990
9-bit x 64-word FIFO register; 3-state
(1) HC : V
Fig.8
(1) HC : V
Fig.9
HCT: V
HCT: V
Waveforms showing the MR input to DIR, DOR output
propagation delays and the MR pulse width.
Waveforms showing the SO input to DIR output propagation
delay. The SO pulse width and SO maximum pulse frequency.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
13
Notes to Fig.8
1. DIR LOW, output ready HIGH;
2. MR pulse LOW; clears FIFO.
3. DIR goes HIGH; flag indicates
4. DOR drops LOW; flag indicates
Notes to Fig.9
1. DOR HIGH; no data transfer in
2. SO set HIGH; results in DOR
3. DOR drops LOW; output stage
4. SO is set LOW; data in the input
5. DOR goes HIGH; transfer
6. Repeat process to unload the 3rd
7. DOR remains LOW; FIFO is
assume FIFO is full.
input prepared for valid data.
FIFO empty.
progress, valid data is present at
output stage.
going LOW.
“busy”.
stage is unloaded, and new data
replaces it as empty location
“bubbles-up” to input stage.
process completed, valid data
present at output after the
specified propagation delay.
through to the 64th word from
FIFO.
empty.
74HC/HCT7030
Product specification