74HCT7030D,112 NXP Semiconductors, 74HCT7030D,112 Datasheet - Page 2

• Manufacturer Part Number: 74HCT7030D,112
• Description: IC 9X64 FIFO REGISTER 3ST 28SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT7030D,112

• Function: Asynchronous, Synchronous
• Memory Size: 576 (9 x 64)
• Data Rate: 33MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Logic Family: HCT
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 9
• Number Of Inputs: 9
• Number Of Outputs: 9
• High Level Output Current: -6mA
• Low Level Output Current: 6mA
• Propagation Delay Time: 117ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 36(Typ)MHz
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 50uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-2900-5; 933798900112

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT7030 are high-speed Si-gate CMOS
devices specified in compliance with JEDEC standard
no. 7A.
The 74HC/HCT7030 is an expandable, First-In First-Out
(FIFO) memory organized as 64 words by 9 bits. A 33 MHz
data-rate makes it ideal for high-speed applications. Even
at high frequencies, the I
(f
80 mA). If the device is not continuously operating at f
then I
With separate controls for shift-in (SI) and shift-out (SO),
reading and writing operations are completely
independent, allowing synchronous and asynchronous
data transfers. Additional controls include a master-reset
input (MR) and an output enable input (OE). Flags for
data-in-ready (DIR) and data-out-ready (DOR) indicate the
status of the device.
Devices can be interconnected easily to expand word and
bit dimensions. All output pins are directly opposite the
corresponding input pins thus simplifying board layout in
expanded applications.
INPUTS AND OUTPUTS
Data inputs (D
As there is no weighting of the inputs, any input can be
assigned as the MSB. The size of the FIFO memory can
be reduced from the 9
7
V
December 1990
max
CC
Synchronous or asynchronous operation
3-state outputs
Master-reset input to clear control functions
33 MHz (typ.) shift-in, shift-out rates with or without flags
Very low power consumption
Cascadable to 25 MHz (typ.)
Readily expandable in word and bit dimensions
Pinning arranged for easy board layout: input pins
directly opposite output pins
Output capability: standard
I
9-bit x 64-word FIFO register; 3-state
CC
64, down to 1
or GND.
= 18 MHz; V
CC
category: LSI
will decrease proportionally.
0
to D
CC
64, by tying unused data input pins to
= 5 V produces a dynamic I
8
)
64 configuration, i.e. 8
CC
dynamic is very low
CC
64,
of
max
,
2
Data outputs (Q
As there is no weighting of the outputs, any output can be
assigned as the MSB. The size of the FIFO memory can
be reduced from the 9
data inputs. In a reduced format, the unused data output
pins must be left open circuit.
Master-reset (MR)
When MR is LOW, the control functions within the FIFO
are cleared, and data content is declared invalid. The
data-in-ready (DIR) flag is set HIGH and the
data-out-ready (DOR) flag is set LOW. The output stage
remains in the state of the last word that was shifted out,
or in the random state existing at power-up.
Status flag outputs (DIR, DOR)
Indication of the status of the FIFO is given by two status
flags, data-in-ready (DIR) and data-out-ready (DOR):
Shift-in control (SI)
Data is loaded into the input stage on a LOW-to-HIGH
transition of SI. A HIGH-to-LOW transition triggers an
automatic data transfer process (ripple through). If SI is
held HIGH during reset, data will be loaded at the rising
edge of the MR signal.
Shift-out control (SO)
A LOW-to-HIGH transition of SO causes the DOR flags to
go LOW. A HIGH-to-LOW transition of SO causes
upstream data to move into the output stage, and empty
locations to move towards the input stage (bubble-up).
Output enable (OE)
The outputs Q
OE = HIGH the outputs are in the high impedance
OFF-state.
DIR
DIR
DOR = HIGH assures valid data is present at the
DOR = LOW indicates the output stage is busy or
= HIGH indicates the input stage is empty and
= LOW indicates that the FIFO is full or that a
ready to accept valid data
previous shift-in operation is not complete
(busy)
outputs Q
data is awaiting transfer into the output stage)
there is no valid data
0
to Q
0
to Q
8
0
are enabled when OE = LOW. When
to Q
8
)
64 configuration as described for
8
(does not indicate that new
74HC/HCT7030
Product specification