LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 385

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LM3S1150-IQC50-A1

Manufacturer Part Number
LM3S1150-IQC50-A1
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
PWM Output Inversion (PWMINVERT)
Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
June 14, 2007
Reset
Reset
Type
Type
Bit/Field
31:6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the PWM generator are active High; they can optionally be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive channels maintain the correct polarity.
RO
RO
30
14
0
0
PWM5Inv
PWM4Inv
PWM3Inv
PWM2Inv
PWM1Inv
PWM0Inv
reserved
Name
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
reserved
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
RO
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, the generated PWM5 signal is inverted.
When set, the generated PWM4 signal is inverted.
When set, the generated PWM3 signal is inverted.
When set, the generated PWM2 signal is inverted.
When set, the generated PWM1 signal is inverted.
When set, the generated PWM0 signal is inverted.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
PWM5Inv
R/W
RO
21
0
5
0
PWM4Inv
R/W
RO
20
0
4
0
PWM3Inv
LM3S1150 Microcontroller
R/W
RO
19
0
3
0
PWM2Inv
R/W
RO
18
0
2
0
PWM1Inv
R/W
RO
17
0
1
0
PWM0Inv
R/W
RO
16
0
0
0
385

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