LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 394

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Pulse Width Modulator (PWM)
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
Type R/W1C, reset 0x0000.0000
394
Reset
Reset
Type
Type
Bit/Field
31:6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C PWM1
Interrupt Status and Clear (PWM1ISC), offset 0x08C PWM2 Interrupt Status
and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events
that have occurred; a 0 bit indicates that the event in question has not occurred. These are R/W1C
registers; writing a 1 to a bit position clears the corresponding interrupt reason.
RO
RO
30
14
0
0
IntCntLoad
IntCntZero
IntCmpBD
IntCmpBU
IntCmpAD
IntCmpAU
reserved
Name
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
RO
RO
Type
27
11
0
0
RO
reserved
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
RO
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Indicates that the counter has matched the comparator B value while
counting down.
Indicates that the counter has matched the comparator B value while
counting up.
Indicates that the counter has matched the comparator A value while
counting down.
Indicates that the counter has matched the comparator A value while
counting up.
Indicates that the counter has matched the PWMnLOAD register.
Indicates that the counter has matched 0.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
IntCmpBD
R/W1C
RO
21
0
5
0
IntCmpBU
R/W1C
RO
20
0
4
0
IntCmpAD
R/W1C
RO
19
0
3
0
IntCmpAU
R/W1C
RO
18
0
2
0
June 14, 2007
IntCntLoad
R/W1C
RO
17
0
1
0
IntCntZero
R/W1C
RO
16
0
0
0