LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 129

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LM3S1150-IQC50

Manufacturer Part Number
LM3S1150-IQC50
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet

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Hibernation RTC Trim (HIBRTCT)
Offset 0x024
Type R/W, reset 0x0000.0000
June 14, 2007
Reset
Reset
Type
Type
Bit/Field
31:16
15:0
R/W
RO
31
15
0
0
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.
R/W
RO
30
14
0
1
reserved
Name
TRIM
R/W
RO
29
13
0
1
Luminary Micro Confidential-Advance Product Information
R/W
RO
28
12
0
1
R/W
RO
Type
27
11
R/W
0
1
RO
R/W
RO
26
10
0
1
0x7FFF
0x0000
Reset
R/W
RO
25
0
9
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.
R/W
RO
24
0
8
1
reserved
TRIM
R/W
RO
23
0
7
1
R/W
RO
22
0
6
1
R/W
RO
21
0
5
1
R/W
RO
20
0
4
1
LM3S1150 Microcontroller
R/W
RO
19
0
3
1
R/W
RO
18
0
2
1
R/W
RO
17
0
1
1
R/W
RO
16
0
0
1
129

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