LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 82

• Manufacturer Part Number: LM3S1150-IQC50
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0010.30DF
82
Reset
Reset
Type
Type
Bit/Field
31:21
19:16
15:12
11:8
20
7
6
5
4
3
RO
RO
31
15
0
0
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. The PWM, SARADC0,
MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers.
Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1.
RO
RO
30
14
0
0
SYSDIV
reserved
reserved
reserved
reserved
SYSDIV
Name
PWM
MPU
WDT
PLL
HIB
RO
RO
29
13
0
1
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
1
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
reserved
Reset
0x3
0
1
0
0
1
1
0
1
1
RO
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
When set, indicates that the Hibernation module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
When set, indicates that a watchdog timer is present.
RO
RO
Value
0x3
24
0
8
0
Description
Specifies a 50-MHz CPU clock with a PLL divider of 4.
MPU
RO
RO
23
0
7
1
HIB
RO
RO
22
0
6
1
reserved
RO
RO
21
0
5
0
PWM
PLL
RO
RO
20
1
4
1
WDT
RO
RO
19
0
3
1
SWO
RO
RO
18
0
2
1
reserved
June 14, 2007
SWD
RO
RO
17
0
1
1
JTAG
RO
RO
16
0
0
1