LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 428

• Manufacturer Part Number: LM3S1150-IQC50
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Signal Tables
428
Pin Name
I2C0SCL
I2C0SDA
CMOD0
CMOD1
Fault
CCP4
CCP5
GNDA
GNDA
IDX0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HIB
LDO
NC
NC
NC
NC
NC
NC
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Pin Number
100
35
25
65
76
99
15
21
33
39
45
54
57
63
69
82
87
94
97
51
70
71
16
17
36
37
40
41
9
4
7
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
Buffer Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
OD
OD
-
-
-
-
-
-
Description
Capture/Compare/PWM 1
Capture/Compare/PWM 5
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
PWM Fault
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
An output that indicates the processor is in
hibernate mode.
I2C module 0 clock
I2C module 0 data
QEI module 0 index
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
No connect
No connect
No connect
No connect
No connect
No connect
June 14, 2007