LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 209

• Manufacturer Part Number: LM3S1150-IQC50
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0x0000.0000
June 14, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
1:0
3
2
RO
RO
31
15
0
0
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
RO
RO
30
14
0
0
reserved
TBAMS
TBCMR
TBMR
Name
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
0
0
0
0
RO
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB Alternate Mode Select
0: Capture mode is enabled.
1: PWM mode is enabled.
Note:
GPTM TimerB Capture Mode
0: Edge-Count mode.
1: Edge-Time mode.
GPTM TimerB Mode
0x0: Reserved.
0x1: One-Shot Timer mode.
0x2: Periodic Timer mode.
0x3: Capture mode.
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
To enable PWM mode, you must also clear the TBCMR bit and
set the TBMR field to 0x2.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S1150 Microcontroller
TBAMS
R/W
RO
19
0
3
0
TBCMR
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
TBMR
R/W
RO
16
0
0
0
209