LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 220
![no-image](/images/no-image-200.jpg)
LM3S1150-IQC50
Manufacturer Part Number
LM3S1150-IQC50
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S1150-IQC50.pdf
(471 pages)
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LM3S1150-IQC50-A2
Manufacturer:
Texas Instruments
Quantity:
135
Company:
Part Number:
LM3S1150-IQC50-A2T
Manufacturer:
Texas Instruments
Quantity:
10 000
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General-Purpose Timers
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
220
Reset
Reset
Type
Type
Bit/Field
31:16
15:0
R/W
R/W
31
15
0
1
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
R/W
R/W
30
14
1
1
TAMRH
TAMRL
Name
R/W
R/W
29
13
1
1
Luminary Micro Confidential-Advance Product Information
R/W
R/W
28
12
0
1
R/W
R/W
Type
27
11
R/W
R/W
1
1
R/W
R/W
0x0000 (16-bit
26
10
(32-bit mode)
0
1
0xFFFF
0xFFFF
mode)
Reset
R/W
R/W
25
1
9
1
Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
R/W
R/W
24
1
8
1
TAMRH
TAMRL
R/W
R/W
23
1
7
1
R/W
R/W
22
1
6
1
R/W
R/W
21
0
5
1
R/W
R/W
20
1
4
1
R/W
R/W
19
1
3
1
R/W
R/W
18
1
2
1
June 14, 2007
R/W
R/W
17
1
1
1
R/W
R/W
16
0
0
1
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