FDC37C665IR SMSC Corporation, FDC37C665IR Datasheet - Page 123
FDC37C665IR
Manufacturer Part Number
FDC37C665IR
Description
3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
Manufacturer
SMSC Corporation
Datasheet
1.FDC37C665IR.pdf
(162 pages)
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CR0
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 00H. The default
BIT NO.
5,6
0
1
2
3
4
7
IDE ENABLE
IDE AT/XT
RESR
FDC POWER
FDC ENABLE
OSC
VALID
BIT NAME
A high level on this bit, enables the IDE (Default). A low level on
this bit disables the IDE.
A high level on this bit sets the IDE to AT type (Default). A low
level on this bit sets the IDE to XT type.
(This bit is Reserved - set to '0').
A high level on this bit, supplies power to the FDC (default for the
FDC37C665IR).
power mode.
A high level on this bit, enables the FDC (Default). A low level on
this bit disables the FDC.
6 5
0 0Osc ON, Baud Rate Generator (BRG) Clock Enabled.
0 1Osc is On, BRG Clock is ON when PWRGD is active. When
1 0(same as 0 1 case)
1 1Osc OFF, BR Generator Clock Disabled
A high level on this software controlled bit indicates that a valid
configuration cycle has occurred. The control software must take
care to set this bit at the appropriate times. Set to zero after
power up.
Table 49 - CR0
PWRGD is inactive, Osc is off and BRG Clock is
Disabled (Default).
123
value of this register after power up is 3BH for
the FDC37C665IR.
A low level on this bit puts the FDC in low
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