FDC37C665IR SMSC Corporation, FDC37C665IR Datasheet - Page 155

• Manufacturer Part Number: FDC37C665IR
• Description: 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
• Manufacturer: SMSC Corporation

The Reverse Data Transfer Phase may be
entered from the Reverse-Idle Phase. After the
previous byte has beed accepted the host sets
HostAck (nAutoFd) low. The peripheral then sets
PeriphClk (nAck) low when it has data to send.
The data must be stable for the specified setup
time prior to the falling edge of PeriphClk. When
the host is ready it to accept a byte it sets.
HostAck (nAutoFd) high to acknowledge the
handshake. The peripheral then sets PeriphClk
(nAck) high. After the host has accepted the
data it sets HostAck (nAutoFd) low, completing
the transfer. This sequence is shown in Figure
23.
155
Output Drivers
To facilitate higher performance data transfer,
the use of balanced CMOS active drivers for
critical
PeriphAck, PeriphClk) are used ECP Mode.
Because the use of active drivers can present
compatibility problems in Compatible Mode (the
control signals, by tradition, are specified as
open-collector), the drivers are dynamically
changed from open-collector to totem-pole. The
timing for the dynamic driver change is specified
in the IEEE 1284 Extended Capabilities
Protocol and
1.09, Jan. 7, 1993, available from Microsoft.
The
implemented properly to prevent glitching the
outputs.
dynamic
signals
ISA
driver
(Data,
Interface Standard, Rev.
change
HostAck,
must
HostClk,
Port
be