FDC37C665IR SMSC Corporation, FDC37C665IR Datasheet - Page 130

• Manufacturer Part Number: FDC37C665IR
• Description: 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
• Manufacturer: SMSC Corporation

CR6
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 06H. The default
value of this register after power up is FFH.
This register holds the floppy disk drive types for
up to four floppy disk drives.
CR7
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 07H. The default
value of this register after power up is 00H. This
register holds the value for the auto power
management, floppy boot drive and the polarity
of the media ID bits (see Table 56).
CR8
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 08H. The default
value of this register after power up is 00H. This
is the lower 8 bits for the ADRx address decode.
(Note: All addresses are qualified with AEN.)
CR9
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 09H. The default
value of this register after power up is 00H. This
is the upper 3 bits (D2 - MSB, D0 - LSB) for the
ADRx address decode.
selected then A10 is assumed to be low. (Note:
All addresses are qualified with AEN.)
If ECP mode is not
130
CRA
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0AH. The default
value of this register after power up is 00H. This
byte defines the FIFO threshold for the ECP
mode parallel port.
CRB
This register indicates the data rate table used
for each drive (see Table 57).
CRC
This register determines the status of the two
UARTs as shown in Table 58.
CRD
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0DH. This register
is read only. The default value of this register
after power up is 065H for the FDC37C665IR.
CRE
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0EH. This register
is read only. The default value of this register
after power up is 82H. This is used to identify
the chip revision level.
CRF
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0FH. The default
value of this register after power up is 00H (see
Table 59).