FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 158

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

PME Control
Default = 0x00 on
VTR POR
PME Status
Default = 0x00 on
VTR POR
PME Wake Status
Default = 0x00 on
VTR POR
PME Wake Enable
Default = 0x00 on
V
TR
POR
NAME
Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
(R/w Clear)
(R/w Clear)
(R/W)
(R/W)
0xC5
0xC6
0xC7
0xC8
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by VCC POR, SOFT RESET
or HARD RESET
Bit[0] PME_Status
= 0 (default)
= 1 Set when FDC37M81x would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT
RESET or HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
FDC37M81x to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] Reserved
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[7:5] Reserved
The PME Wake Status register is not affected by VCC
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[4:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
This register is used to enable individual FDC37M81x
PME wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake
event and the PME_En bit is “1”, the source will assert
the PCI nIO_PME signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status register
will indicate the state of the wake source but will not
assert the PCI nIO_PME signal.
PCI nIO_PME signal, independent of the state of
the PME_En bit.
nIO_PME signal assertion is disabled (default)
Enables FDC37M81x to assert nIO_PME signal
158
DEFINITION
STATE